公开(公告)号：DE69308131T2

公开(公告)日：1997-05-28

申请号：DE69308131

申请日：1993-08-18

Applicant: CONS RIC MICROELETTRONICA

Inventor： AIELLO NATALE ,  PALARA SERGIO ,  SCACCIANOCE SALVATORE

IPC: H03G11/00 ,  H03K17/0812 ,  H03K17/082 ,  H03K17/16 ,  H03K17/08

公开(公告)号：DE69518064T2

公开(公告)日：2000-12-21

申请号：DE69518064

申请日：1995-03-22

Applicant: CONS RIC MICROELETTRONICA

Inventor： AIELLO NATALE ,  GRAZIANO VITO

IPC: H01L27/06 ,  H01L21/8222 ,  H01L27/02 ,  H03K17/735 ,  H01L29/00

Abstract: Junction isolation between a second region (2) that is normally clamped at a reference potential, contained within a first region (1) of an opposite type of conductivity whose potential (V1) is subject to large inertial swings is ensured even when the potential of said first region (1) moves toward and beyond the reference potential to which said second region (2) is clamped by clamping said second region (2) to said reference potential by a switch (T) causing the switch (T) to open thus placing the second region (2) in a floating state free to track the potential excursion of the first region (1) and closing again the switch (T) after the potential of the first region (1) has returned to a normal value. A comparator senses a shift of the potential of the second region (2) from the reference potential to which is clamped which is dynamically induded by the capacitive coupling of the two regions, and triggers off the clamping switch (T).

公开(公告)号：DE69614831D1

公开(公告)日：2001-10-04

申请号：DE69614831

申请日：1996-05-21

Applicant: CONS RIC MICROELETTRONICA

Inventor： AIELLO NATALE ,  PATTI DAVIDE ,  LEONARDI SALVATORE ,  SCACCIANOCE SALVATORE

IPC: H01L27/00 ,  H01L27/07 ,  H01L27/082

公开(公告)号：DE69517948T2

公开(公告)日：2001-03-08

申请号：DE69517948

申请日：1995-02-28

Applicant: CONS RIC MICROELETTRONICA

Inventor： AIELLO NATALE

IPC: H01L27/06 ,  H01L21/8222 ,  H01L27/02 ,  H03K19/003

Abstract: A circuit (30) for biasing epitaxial wells of a semiconductor integrated circuit comprises a first transistor (T1) and a second transistor (T2) driven in phase opposition to the first; when the supply voltage is positive, the first transistor (T1), being connected between the power supply and the epitaxial well, is conducting whereas the second transistor (T2) is cut off. When, on the contrary, the supply voltage is negative, the second transistor (T2), being connected between the epitaxial well and the ground reference GND, goes into saturation, thereby holding the epitaxial well biased to ground since, at that time, it is the highest potential present on the device. In this way, it becomes possible to always ensure reverse biasing of the parasitic diodes which form at the junctions between the epitaxial wells and the adjacent regions thereto.

公开(公告)号：DE69518064D1

公开(公告)日：2000-08-24

申请号：DE69518064

申请日：1995-03-22

Applicant: CONS RIC MICROELETTRONICA

Inventor： AIELLO NATALE ,  GRAZIANO VITO

IPC: H01L27/06 ,  H01L21/8222 ,  H01L27/02 ,  H03K17/735 ,  H01L29/00

Abstract: Junction isolation between a second region (2) that is normally clamped at a reference potential, contained within a first region (1) of an opposite type of conductivity whose potential (V1) is subject to large inertial swings is ensured even when the potential of said first region (1) moves toward and beyond the reference potential to which said second region (2) is clamped by clamping said second region (2) to said reference potential by a switch (T) causing the switch (T) to open thus placing the second region (2) in a floating state free to track the potential excursion of the first region (1) and closing again the switch (T) after the potential of the first region (1) has returned to a normal value. A comparator senses a shift of the potential of the second region (2) from the reference potential to which is clamped which is dynamically induded by the capacitive coupling of the two regions, and triggers off the clamping switch (T).

公开(公告)号：DE69127359T2

公开(公告)日：1998-03-19

申请号：DE69127359

申请日：1991-06-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： AIELLO NATALE ,  PALARA SERGIO

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/082 ,  H03K17/00 ,  H03K17/0814 ,  H03K17/30 ,  H03K17/62 ,  H03K19/094

Abstract: In a switching circuit suitable for connecting a first circuit node (1) to a second (2) or to a third (3) circuit node in relation to the latter's potential, particularly for controlling the potential of an insulation region of an integrated circuit in relation to the substrate's potential, there is a first NPN bipolar transistor (T1) with the function of a switch having the collector connected to the first circuit node (1) and the emitter connected to the second circuit node (2) and a second NPN bipolar transistor (T2) with the function of a switch having the collector connected to the first circuit node (1) and the emitter connected to the third circuit node (3). There are means (D1, T5, T6) for maintaining the base of the second transistor (T2) at a constant pre-set bias voltage.

公开(公告)号：DE69530216D1

公开(公告)日：2003-05-08

申请号：DE69530216

申请日：1995-12-19

Applicant: CONS RIC MICROELETTRONICA

Inventor： AIELLO NATALE ,  LA BERBERA ATANASIO ,  LEONARDI SALVATORE

IPC: H01L21/761 ,  H01L27/06

Abstract: A monolithic semiconductor device having an edge structure, which comprises, on a substrate of a first type of doping, a control region (1) of a second type of doping, which is provided with an edge region (2), and a power region of a second type of doping, the particularity whereof resides in that in the edge region at least one channel (8, 9, 10, 11) is provided which is adapted to divide the edge region (2) into regions that are electrically isolated from each other (2, 2a, 2b; 2c, 2d), the region at the channel being covered with a field plate (6). A method for producing the edge structure in combination with the execution of the monolithic device is also disclosed herein.

公开(公告)号：DE69530216T2

公开(公告)日：2004-02-12

申请号：DE69530216

申请日：1995-12-19

Applicant: CONS RIC MICROELETTRONICA

Inventor： AIELLO NATALE ,  LA BERBERA ATANASIO ,  LEONARDI SALVATORE

IPC: H01L21/761 ,  H01L27/06

Abstract: A monolithic semiconductor device having an edge structure, which comprises, on a substrate of a first type of doping, a control region (1) of a second type of doping, which is provided with an edge region (2), and a power region of a second type of doping, the particularity whereof resides in that in the edge region at least one channel (8, 9, 10, 11) is provided which is adapted to divide the edge region (2) into regions that are electrically isolated from each other (2, 2a, 2b; 2c, 2d), the region at the channel being covered with a field plate (6). A method for producing the edge structure in combination with the execution of the monolithic device is also disclosed herein.

公开(公告)号：DE69521210D1

公开(公告)日：2001-07-12

申请号：DE69521210

申请日：1995-12-29

Applicant: CONS RIC MICROELETTRONICA

Inventor： AIELLO NATALE ,  GRAZIANO VITO

IPC: H01L27/02 ,  H01L27/082 ,  H01L29/00

Abstract: The present invention relates to an electronic device integrated monolithically on a semiconductor material comprising a substrate (1) having a first conductivity type in which are formed a first (2) and second diffusion regions (3) of a second conductivity type with said substrate (1) and said first (2) and second (3) diffusion regions including respectively a base region, a collector region and an emitter region of a transistor (Tp1) and characterized in that in the second diffusion region (3) is formed a third diffusion region (8) having conductivity of the first type to provide in said second diffusion region (3) a resistive path (R) placed in series with the emitter region of the transistor (Tp1) while backfeeding it negatively and taking it to saturation with a resulting reduction of its current gain and limitation of the maximum current due thereto.

公开(公告)号：DE69126618T2

公开(公告)日：1998-01-08

申请号：DE69126618

申请日：1991-11-25

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： PAPARO MARIO ,  AIELLO NATALE

IPC: H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H02J1/00 ,  H01L21/76

Abstract: The device consists of a bridge having at least two arms (1, 2) each formed of a first and a second diode-connected transistor (T11, T12; T21, T22). In the integrated monolithic embodiment each arm is formed by a type N+ substrate (3) connected to a positive potential output terminal (K1), type N- and N epitaxial layers (4, 19), type P, P+ regions (5,45; 6,46) contained within the epitaxial layers (4, 19) and containing within them a type N region (7; 8) which in turn contains a type P region (9; 10) connected to a negative potential output terminal (A1). Between the type P, P+ regions (5, 45; 6, 46) belonging to the first and the second arm (1, 2) there are first type N++ regions (11; 12) capable of minimising the current gain of the parasitic transistors (TP1a, TP1b) placed between the type P, P+ regions (5, 45; 6, 46) and second regions (13, 14) of type P and P+ respectively recovering the residual loss currents of the parasitic transistors (TP1a, TP1b).