公开(公告)号：EP1333504A3

公开(公告)日：2007-01-31

申请号：EP03075163.0

申请日：2003-01-17

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Logsdon, James H. ,  Chilcott, Dan W. ,  Lee, Han-Sheng ,  Lambert, David K. ,  Vas, Timothy A.

IPC: H01L35/02 ,  H01L35/08

CPC classification number: G01J5/14 ,  G01J5/12

Abstract: An integrated sensor (10) comprising a thermopile transducer (12) and signal processing circuitry (4) that are combined on a single semiconductor substrate (20), such that the transducer output signal is sampled in close vicinity by the processing circuitry (14). The sensor (10) comprises a frame (18) formed of a semiconductor material that is not heavily doped, and with which a diaphragm (16) is supported. The diaphragm (16) has a first surface for receiving thermal (e.g., infrared) radiation, and comprises multiple layers that include a sensing layer containing at least a pair of interlaced thermopiles (22). Each thermopile (22) comprises a sequence of thermocouples (24), each thermocouple (24) comprising dissimilar electrically-resistive materials that define hot junctions (26) located on the diaphragm (16) and cold junctions (28) located on the frame (18). The signal processing circuitry (14) is located on the frame (18) and electrically interconnected with the thermopiles (22). The thermopiles (22) are interlaced so that the output of one of the thermopiles (22) increases with increasing temperature difference between the hot and cold junctions (26,28) thereof, while the output of the second thermopile (22) decreases with increasing temperature difference between its hot and cold junctions (26,28).

公开(公告)号：EP1724560A1

公开(公告)日：2006-11-22

申请号：EP06075977.6

申请日：2006-05-01

Applicant: Delphi Technologies, Inc.

Inventor： Manlove, Gregory J. ,  Castillo-Borelly, Pedro E. ,  Logsdon, James H.

IPC: G01J5/16

CPC classification number: G01J5/16

Abstract: An infrared temperature sensing device (10) is provided for sensing temperature of a target object. The sensing device (10) includes a semiconductor substrate (16), a thermopile infrared sensor (12) mounted to the substrate (16) for sensing temperature of a remote target object, and temperature sensing circuitry (20) mounted to the substrate (16). The temperature sensing circuitry (20) generates a temperature dependent signal (PTATOUT) substantially linearly related to ambient temperature of the substrate (16). The sensing device (10) further includes summing circuitry (22) for generating a signal (V OUT ) indicative of infrared sensed temperature as a function of the ambient temperature.

Abstract translation: 提供一种用于感测目标物体的温度的红外温度检测装置（10）。 感测装置（10）包括半导体衬底（16），安装到用于感测远程目标物体的温度的衬底（16）的热电堆红外传感器（12）和安装到衬底（16）的温度感测电路（20） ）。 温度感测电路（20）产生与衬底（16）的环境温度基本线性相关的与温度相关的信号（PTATOUT）。 感测装置（10）还包括用于产生指示作为环境温度的函数的红外感测温度的信号（V OUT）的求和电路（22）。

公开(公告)号：EP1582499A2

公开(公告)日：2005-10-05

申请号：EP05075730.1

申请日：2005-03-29

Applicant: Delphi Technologies, Inc.

Inventor： Chase, Troy A. ,  Logsdon, James H. ,  Kingery, Edward J.

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00333 ,  B81C2203/0118

Abstract: A method of processing a wafer, and particularly a cap wafer (10) configured for mating with a device wafer in the production of a die package (64). Masking layers (20,22) are deposited on oxide layers (16,18) present on opposite surfaces of the wafer (10), after which the masking layers (20,22) are etched to expose regions (32,34,40) of the underlying oxide layers (16,18). Thereafter, an oxide mask (42) is formed on the exposed regions (32,34,40) of the oxide layers (16,18), but is prevented from forming on other regions (44,45,46) of the oxide layers (16,18) masked by the masking layers (20,22). The masking layers (20,22) are then removed and the underlying regions (44,45,46) of the oxide layers (16,18) and the wafer (10) are etched to simultaneously produce through-holes (48) and recesses (50) in the wafer (10). The oxide mask (42) is then removed to allow mating of the cap wafer (10) with a device wafer.

Abstract translation: 一种处理晶片的方法，特别是在晶片封装（64）的制造中被配置为与器件晶片配合的盖晶片（10）。 屏蔽层（20,22）沉积在存在于晶片（10）的相对表面上的氧化物层（16,18）上，之后蚀刻掩模层（20,22）以暴露区域（32,34,40） 的下面的氧化物层（16,18）。 此后，氧化物掩模（42）形成在氧化物层（16,18）的暴露区域（32,34,40）上，但是防止在氧化物层（16,18）的其它区域（44,45,46）上形成氧化物掩模 （16,18）被掩蔽层（20,22）掩蔽。 然后去除掩模层（20,22），并且蚀刻氧化物层（16,18）和晶片（10）的下面的区域（44,45,46）以同时产生通孔（48）和凹槽 （50）在晶片（10）中。 然后去除氧化物掩模（42）以允许盖晶片（10）与器件晶片的配合。