公开(公告)号：DE2459532A1

公开(公告)日：1975-12-11

申请号：DE2459532

申请日：1974-12-17

Applicant: IBM

Inventor： ANACKER WILHELM

IPC: H01L25/00 ,  H01L23/532 ,  H01L23/538 ,  H01L39/00 ,  H01L39/02 ,  H01L23/46 ,  H01L23/50 ,  H01L39/04 ,  H05K1/14

Abstract: A three dimensional micro electronic module packaged for reduced signal propagation delay times includes a plurality of circuit carrying means, which may comprise unbacked chips, with integrated superconductive circuitry thereon. The circuit carrying means are supported on their edges and have contact lands in the vicinity of, or at, the edges to provide for interconnecting circuitry. The circuit carrying means are supported by supporting means which include slots to provide a path for interconnection wiring to contact the lands of the circuit carrying means. Further interconnecting wiring may take the form of integrated circuit wiring on the reverse side of the supporting means. The low heat dissipation of the superconductive circuitry allows the circuit carrying means to be spaced approximately no less than 30 mils apart. The three dimensional arrangement provides lower random propagation delays than would a planar array of circuits.

公开(公告)号：DE2330731A1

公开(公告)日：1974-01-10

申请号：DE2330731

申请日：1973-06-16

Applicant: IBM

Inventor： ANACKER WILHELM ,  MATISOO JURI

IPC: H01L27/18 ,  H01L39/22 ,  H03K3/38 ,  H03K17/92 ,  H03K19/195 ,  H03K19/02

Abstract: Superconductive circuitry using a first Josephson tunneling device connected to a transmission line having a termination such that no reflections result when the Josephson tunneling diode switches between two stable voltage states, in accordance with applied input signals. Means are provided for producing the input signals to switch the first Josephson tunneling device and further Josephson tunneling devices are provided whose voltage state depends on the current pulse delivered to the transmission line when the first Josephson tunneling device switches from a first voltage state to a second voltage state. Logic circuitry is shown using this structure, as well as fan-in and fan-out Josephson tunneling device circuits.

公开(公告)号：CA1024660A

公开(公告)日：1978-01-17

申请号：CA223589

申请日：1975-03-27

Applicant: IBM

Inventor： ANACKER WILHELM

IPC: H01L25/00 ,  H01L23/532 ,  H01L23/538 ,  H01L39/00 ,  H01L39/02 ,  H05K1/02

Abstract: A three dimensional micro electronic module packaged for reduced signal propagation delay times includes a plurality of circuit carrying means, which may comprise unbacked chips, with integrated superconductive circuitry thereon. The circuit carrying means are supported on their edges and have contact lands in the vicinity of, or at, the edges to provide for interconnecting circuitry. The circuit carrying means are supported by supporting means which include slots to provide a path for interconnection wiring to contact the lands of the circuit carrying means. Further interconnecting wiring may take the form of integrated circuit wiring on the reverse side of the supporting means. The low heat dissipation of the superconductive circuitry allows the circuit carrying means to be spaced approximately no less than 30 mils apart. The three dimensional arrangement provides lower random propagation delays than would a planar array of circuits.

公开(公告)号：CA907197A

公开(公告)日：1972-08-08

申请号：CA907197D

Applicant: IBM

Inventor： ANACKER WILHELM

IPC: G11C11/44 ,  H01L39/22 ,  H03K3/38 ,  H03K19/195

公开(公告)号：CA865871A

公开(公告)日：1971-03-09

申请号：CA865871D

Applicant: IBM

Inventor： WANG CHU P ,  ANACKER WILHELM

公开(公告)号：DE3068906D1

公开(公告)日：1984-09-13

申请号：DE3068906

申请日：1980-11-20

Applicant: IBM

Inventor： AMES IRVING ,  ANACKER WILHELM ,  GREBE KURT RUDOLPH ,  KIRCHER CHARLES JOHN

IPC: H01L27/18 ,  H01L23/485 ,  H01L23/532 ,  H01L39/02 ,  H01L39/22

Abstract: Circuit connection for electrical circuitry, and particularly superconducting circuits including Josephson tunnelling devices, wherein solder lands can be used to make electrical connection to electric lines without interdiffusion between the lines and the solder. … To avoid the interdiffusion problem, a laterally extending metallic layer (18) is used as a diffusion barrier between the solder land (28) and the electrical line (M) which can be a superconducting line. The diffusion layer is comprised of refractory metal and has a first portion electrically contacting the solder land and a second, laterally displaced portion, electrically contacting the electrical line. An insulating layer (22) on the diffusion barrier layer separates the solder land and the electrical line. In a specific embodiment, the diffusion barrier is comprised of niobium, and the solder is a low melting point alloy, typically comprised of indium, bismuth, and tin.

公开(公告)号：CA1142264A

公开(公告)日：1983-03-01

申请号：CA365924

申请日：1980-12-02

Applicant: IBM

Inventor： AMES IRVING ,  ANACKER WILHELM ,  GREBE KURT R ,  KIRCHER CHARLES J

IPC: H01L27/18 ,  H01L23/485 ,  H01L23/532 ,  H01L39/02 ,  H01L39/22

Abstract: CONTACT TECHNIQUE FOR ELECTRICAL CIRCUITRY . In electrical circuitry, and particularly superconducting circuitry including Josephson tunnelling devices, it is often necessary to provide solder contacts to electrical lines, where the electrical lines would be destroyed if there were interdiffusion between the lines and the solder. To avoid this problem, a laterally extending metallic layer is used as a diffusion barrier between the solder land and the electrical line which can be a superconducting line. The diffusion barrier is comprised of a refractory metal which has a first portion electrically contacting the solder land and a second, laterally displaced portion electrically contacting the electrical line. An insulating protective layer on the diffusion barrier layer separates the solder land and the electrical line. In a specific embodiment, the superconducting electrical line is comprised of an alloy of lead while the diffusion barrier is comprised of niobium, and the solder alloy is a low melting point alloy, typically comprised of indium, bismuth,

公开(公告)号：DE1524791A1

公开(公告)日：1970-10-08

申请号：DE1524791

申请日：1967-05-27

Applicant: IBM

Inventor： ANACKER WILHELM

IPC: G11C11/06 ,  G11C29/00 ,  G06F7/24

Abstract: 1,117,970. Defective storage cells; read-only and erasable stores. INTERNATIONAL BUSINESS MACHINES CORP. 28 April, 1967 [15 June, 1966], No. 19608/67. Headings G4A and G4C. [Also in Division H3] A random-access memory system comprises a word-addressable main memory, each word line being divided into sub-words and having associated with it separate cells specifying which of the sub-words contain defective cells and the address of at least one replacement sub-word in a replacement store. Word lines 12 of a main memory 10 are continuations of the word lines of a read-only memory 20, so when a word of the main memory 10 is addressed for read or write, the read-only memory 20 supplies: 16 flag bits specifying which, if any, of the 16 sub-words of the main memory word contain defective bit cells, 16 bits to select a word line of a replacement store 17, 4 bits to select one of 16 subwords of the selected word of the replacement store 17, and 6 check bits (e.g. Hamming code) which are used to correct any errors in the other bits from the read-only memory before use. If all the flag bits are zero (no defective cells in the main memory word), the 20 bits for addressing the replacement store 17 will be zeroes so that no addressing will take place. In a read operation, the addressed main memory word is read out into a one-word transfer register (of flip-flops). If any of the sub-words have defective cells, the relevant replacement word (which may be shared between a plurality of main memory words) is read from the replacement store 17 into a one-word replacement register (of flip-flops). The flag bits cause the sub-word sections of the transfer register fed from defective sub-words of the main memory 10 to be selected in turn to be reset and receive the contents of a sub-word section of the replacement register. The first sub-word section of the replacement register to be used for this purpose is that specified by the read-only memory 20 which sets a counting register to select one of the sections. The other sections used are the successively adjacent sections in the replacement register, obtained by incrementing the counting register as many times as necessary. The contents of the transfer register are finally sent to the computer 32. A write operation is similar except that those subword sections of a word placed in the transfer register by the computer 32 which will be going into defective sub-words of the main memory 10 are copied into the appropriate sub-word sections of the replacement register (these sections having first been reset) before restoring the contents of this register into the replacement store 17. The replacement store 17 could be a part of the main memory 10. Cross-bar switching circuitry could be used to allow a plurality of sub-words to be replaced simultaneously, instead of sequentially as above. Error detection and correction could be associated with the transfer and replacement registers. Construction of memories (Figs. 5, 7).-The main memory 10 and read-only memory 20 are formed on different parts of a common ground plane 110 on which are deposited successive layers of insulation, magnetic film and conductive material forming a laminate 113 including two anisotropic magnetic layers 114, each 800 Š thick. Word lines 12 extend across both the erasable main memory and the read-only memory. The laminate 113 is etched through in the main memory portion 10 to form bitsense lines 11 orthogonal to the word lines 12. In the read-only portion (Fig. 7), transverse sense lines 116, 120 are formed in complementary pairs by selectively etching copper ladder networks on the two sides of a plastic sheet (not shown) so that the sense lines 116, 120, at their intersections with the word lines 12, run parallel or orthogonal to the word lines to store 1 and 0 respectively. Each pair of sense lines is connected to a terminating resistor 122 at one end and feeds a differential amplifier 130 at the other. The word lines 12 include magnetic keeper layers. The main memory 10 could be broken up into a plurality of modules.

公开(公告)号：CA772825A

公开(公告)日：1967-11-28

申请号：CA772825D

Applicant: IBM

Inventor： ANACKER WILHELM

公开(公告)号：DE1934278A1

公开(公告)日：1970-07-23

申请号：DE1934278

申请日：1969-07-05

Applicant: IBM

Inventor： ANACKER WILHELM

IPC: G11C11/44 ,  H01L39/22 ,  H03K19/195

Abstract: 1,244,518. Super-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 27 June, 1969 [15 July, 1968], No. 32500/69. Heading H1K. [Also in Division H3] An information storage cell comprises a pair of Josephson tunnelling devices connected to an input portion, and switch means for switching either one of the pair of devices from the novoltage state (electron pair tunnelling) to the voltage state (single-electron tunnelling). As shown, Fig. 2, a memory cell 10 comprises a word line 12 in which is formed a loop having two identical arms 14, 16, each containing a Josephson junction 18, 20. A bit line 22 passes, over the junctions 18, 20 and a sense line 24 passes under part of the loop remote from the junctions 18, 20 and is provided with a gate in the form of a Josephson junction 26 underlying the loop arm 16. In the rest condition a persistent current circulates in the loop the clockwise and anticlockwise directions representing the " 1 " and " 0 " states respectively. A current IW applied to the word line 12 divides equally between the arms 14, 16 and combines with the stored current resulting in a large net current in one arm in the direction of the stored current and a small net current in the other arm in the opposite direction (IW is greater than the stored current). If a current IB is simultaneously applied to the bit line 22 the critical current of the Josephson junction in the loop arm carrying the large net current will be exceeded and junction will switch to the voltage state if the bit current is in the same direction as the net current. The current is redistributed in the cell resulting in a reversal of the circulating current direction in the loop. If the large net loop arm current and the bit line current are in opposite directions no switching occurs and the circulating current remains unchanged. The final state of the cell is therefore changed to a state corresponding to a circulation direction opposite to the direction of the bit current or allowed to remain in this state depending on the initial state of the cell so that a desired input can be written into the cell. The cell is non-destructively read by applying the word current IW to the line 12 and a sense current to line 24 in a direction from right to left in the Figure. If a " 1 " is stored in the loop a large net current flows in arm 16 and since it is in the same direction as the sense current the Josephson junction 26 in the sense line is switched to its voltage state to provide an output signal. If a " 0 " is stored in the loop the current in arm 16 is small and junction 26 remains in the super-conductive state. The cell may be produced by evaporating a ground plane of super-conductor material on to an insulating substrate, depositing an insulating layer by evaporation or RF sputtering, depositing the bottom portions of the sense line and loop arms through a mask, performing a controlled oxidation or deposition of insulation to form the thin insulating layers for the Josephson junctions and depositing super-conductor material and insulating material alternately to complete the required structure. The superconductor material may be Pb, Sn, Nb or Ta. A Josephson junction decoding tree is described, Fig. 6 (not shown), and such decoders may be combined with a matrix of memory cells to form a random access store, Fig. 7 (not shown). The complete store may be formed on a single substrate by simultaneous deposition.