公开(公告)号：JP2001357071A

公开(公告)日：2001-12-26

申请号：JP2001091839

申请日：2001-03-28

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  HEDDES MARCO C ,  ANTONIOS MARAGUKOSU ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: G06F17/30 ,  H04L12/46 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide novel data structure, method and device for finding out full matching(FM) between a search pattern and a pattern stored in the leaf of a search tree. SOLUTION: A key is inputted, a hash function is executed to a key, a direct table(DT) is accessed, and walk-through of the tree is performed until reaching the leaf through a pattern search control block(PSCB). Both the key and correspondent information required for retrieval are stored in a Patricia tree structure and the hash function performs mapping of n->n from the bit of the key to the bit of a hashed key.

公开(公告)号：CZ20021780A3

公开(公告)日：2002-10-16

申请号：CZ20021780

申请日：2000-11-21

Applicant: IBM ,  IBM UK

Inventor： AYDEMIR METIN ,  BASS BRIAN MITCHELL ,  JEFFRIES CLARK DEBS ,  ROVNER SONIA KIANG ,  SIEGEL MICHAEL STEVEN ,  GALLO ANTHONY MATTEO ,  GORTI BRAHMANAND KUMAR ,  HEDDES MARCO

IPC: H04L47/30 ,  H04L29/06 ,  G06F15/16

Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.

公开(公告)号：AU1406901A

公开(公告)日：2001-06-04

申请号：AU1406901

申请日：2000-11-21

Applicant: IBM ,  IBM UK

Inventor： AYDEMIR METIN ,  BASS BRIAN MITCHELL ,  JEFFRIES CLARK DEBS ,  ROVNER SONIA KIANG ,  SIEGEL MICHAEL STEVEN ,  GALLO ANTHONY MATTEO ,  GORTI BRAHMANAND KUMAR ,  HEDDES MARCO

IPC: H04L47/30 ,  H04L29/06 ,  H04L12/56

Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.

公开(公告)号：HU0203928A2

公开(公告)日：2003-04-28

申请号：HU0203928

申请日：2000-11-21

Applicant: IBM UK ,  IBM

Inventor： AYDEMIR METIN ,  BASS BRIAN MITCHELL ,  GALLO ANTHONY MATTEO ,  GORTI BRAHMANAND KUMAR ,  HEDDES MARCO ,  JEFFRIES CLARK DEBS ,  ROVNER SONIA KIANG ,  SIEGEL MICHAEL STEVEN

IPC: H04L47/30 ,  H04L29/06

Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.

公开(公告)号：DE60042493D1

公开(公告)日：2009-08-13

申请号：DE60042493

申请日：2000-11-21

Applicant: IBM

Inventor： AYDEMIR METIN ,  BASS BRIAN MITCHELL ,  JEFFRIES CLARK DEBS ,  ROVNER SONIA KIANG ,  SIEGEL MICHAEL STEVEN ,  GALLO ANTHONY MATTEO ,  GORTI BRAHMANAND KUMAR ,  HEDDES MARCO

IPC: H04L47/30

Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.

公开(公告)号：AT354830T

公开(公告)日：2007-03-15

申请号：AT00959157

申请日：2000-08-24

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  HEDDES MARCO C ,  PATEL PIYUSH CHUNILAL ,  REVILLA JUAN GUILLERMO ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: G06F15/167 ,  G06F12/06 ,  G06F15/177 ,  H04L12/56 ,  H04Q11/04 ,  G06F15/16 ,  G06F12/00 ,  G06F13/16

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.

公开(公告)号：CA2387101C

公开(公告)日：2006-01-03

申请号：CA2387101

申请日：2000-11-21

Applicant: IBM

Inventor： GALLO ANTHONY MATTEO ,  ROVNER SONIA KIANG ,  SIEGEL MICHAEL STEVEN ,  JEFFRIES CLARK DEBS ,  HEDDES MARCO ,  GORTI BRAHMANAND KUMAR ,  BASS BRIAN MITCHELL ,  AYDEMIR METIN

IPC: H04L47/30

Abstract: Methods, apparatus and program products for controlling a flow of a pluralit y of packets in a computer network are disclosed. The computer network include s a device defining a queue. The methods, apparatus and program products inclu de determining a queue level for the queue and determining an offered rate of t he plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, base d on the queue level, the offered rate and a previous value of the transmissio n fraction so that the transmission fraction and the queue level are criticall y damped if the queue level is between at least a first queue level and a seco nd queue level. Several embodiments are disclosed in which various techniques a re used to determine the manner of the control.

公开(公告)号：AT280411T

公开(公告)日：2004-11-15

申请号：AT00983409

申请日：2000-12-21

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  DAVIS GORDON TAYLOR ,  GALLO ANTHONY MATTEO ,  HEDDES MARCO ,  JENKINS STEVEN KENNETH ,  LEAVENS ROSS BOYD ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: H04L12/28 ,  H04L12/46 ,  H04L12/56 ,  H04L45/60 ,  G06F9/46 ,  H04L29/06

Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.

公开(公告)号：MY121358A

公开(公告)日：2006-01-28

申请号：MYPI9800946

申请日：1998-03-04

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  HUBBARD JAMES ALLISON ,  OMAN PRICE WARD ,  PITA FRANK J

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/40

Abstract: METHOD AND SYSTEM FOR CONTROLLING THE STATE OF A SYSTEM BUS DURING LIVE INSERTION AND REMOVAL OF A PLUGGABLE FEATURE CARD (FC) BY DRIVING CONTROL SIGNALS, WHICH ARE TRANSFERRED OVER THE SYSTEM BUS, TO AN ACTIVE SIGNAL LEVEL, OR BY DRIVING DOWN LEVEL ACTIVE CONTROL SIGNALS TO A LOW SIGNAL LEVEL NEAR GROUND LEVEL. BY THIS MECHANISM, THE SYSTEM BUS BECOMES IMMUNE TO SIGNAL DISTURBANCES AND THEREBY ALLOWS PLUGGABLE UNITS TO BE LIVE INSERTED AND REMOVED WITHOUT CAUSING ADVERSE EFFECTS TO THE SYSTEM SUCH AS A SYSTEM RESET OR COMPROMISE OF DATA INTEGRITY. DURING LIVE INSERTION OR REMOVAL, A LIVE INSERTION BUS CONTROLLER (LIBC) ACQUIRES ACCESS TO THE SYSTEM BUS THROUGH ITS INTERFACE WITH A SYSTEM BUS CONTROLLER (SBC), AFTER IT HAS BEEN SIGNALLED BY A LIVE INSERTION MECHANISM ASSOCIATED WITH THE FC THAT THE FC IS IN THE PROCESS OF BEING LIVE INSERTED OR REMOVED. AFTER SYSTEM BUS ACCESS HAS BEEN ACQUIRED BY THE LIBC AND THE LIBC HAS TAKEN OVER THE CONTROL OF THE SYSTEM BUS, IT DRIVES A SUBSET OF THE SYSTEM BUS SET OF CONTROL SIGNALS TO A STATE THAT IS IMMUNE FROM INSERTION/REMOVAL SIGNAL DISTURBANCE. IN PARALLEL, THE LIBC EFFECTS SUSPENSION OF RUNNING TIMEOUT AND WATCHDOG OPERATIONS CURRENTLY BEING PERFORMED BY THE SBC. WHEN THE LIBC IS INFORMED THAT THE INSERTION PROCESS HAS BEEN COMPLETED, THE SBC AGAIN ACQUIRES CONTROL OF THE SYSTEM BUS. THE SAME PROCEDURAL STEPS ARE PERFORMED IN CASE OF REMOVAL OF AN FC.(FIG. 2)

公开(公告)号：ES2226958T3

公开(公告)日：2005-04-01

申请号：ES00983409

申请日：2000-12-21

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  DAVIS GORDON TAYLOR ,  GALLO ANTHONY MATTEO ,  HEDDES MARCO ,  JENKINS STEVEN KENNETH

IPC: H04L12/28 ,  H04L12/46 ,  H04L12/56 ,  H04L45/60 ,  G06F9/46 ,  H04L29/06

Abstract: Un aparato que comprende: un substrato semiconductor; N unidades (110) de procesamiento fabricadas sobre el substrato, donde N > 1; una primera memoria de datos interna accesible para dichas N unidades de procesamiento; una unidad (112) de expedición acoplada operativamente a las N unidades de procesamiento para recibir y transmitir una unidad de información de entrada a una de las N unidades de procesamiento; una unidad (118) de clasificación acoplada a la unidad (112) de expedición, incluyendo dicha unidad de clasificación una unidad (114) de comparación para determinar un formato de datos para una unidad de información de entrada y para generar y almacenar en la memoria de datos interna indicadores de salida para la unidad de información de entrada, que indican el formato de datos de la unidad de información de entrada y una dirección de arranque para la unidad de información de entrada, cuyos indicadores y dirección de arranque están disponibles para una de las N unidades de procesamiento durante su procesamiento de la unidad de información de entrada y son utilizados en el procesamiento de la unidad de información de entrada; y una unidad (114) de compleción soportada en el substrato semiconductor y conectada operativamente a las N unidades (110) de procesamiento para recibir la unidad de información procesada por la unidad considerada de las N unidades (110) de procesamiento.