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    12.
    发明专利
    未知

    公开(公告)号：SE323545B

    公开(公告)日：1970-05-04

    申请号：SE198166

    申请日：1966-02-16

    Applicant: IBM

    Inventor： WEBER H ,  BEAUSOLEIL W ,  HOSKINSON W ,  KING L

    IPC: G06F13/10 ,  G06F13/12 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177

    Abstract: 1,119,421. Data processors. INTERNATIONAL BUSINESS MACHINES CORP. 18 Jan., 1966 [16 Feb., 1965], No. 2228/66. Heading G4A. Data is transmitted between two data processing devices via a buffer adapter linked to both devices by data and control channels, which also link the data processing devices to respective groups of input/output devices. Two or more computers are linked together and to input-output (I-O) control units (each controlling one or more input-output devices) by one or more adapters. The channels linking a computer to an adapter comprise a 9-wire data channel (8 bits plus 1 parity bit) from the computer (" bus out "), a similar channel to the computer (" bus in "), tag lines in and out indicating the type of information on the associated bus (e.g. data, address, command, status), various interlock lines, a loop enabling the I-O control units to be scanned in turn, and a suppress out line for preventing presentation of status information or data to the computer. When a first computer (any one) requires to send data to a second computer (any other) it sends the address of the appropriate adapter (priority between adapters is also mentioned) which responds by raising an interlock line to the first computer. The latter drops the address signals whereupon the adapter returns the address to the computer which then sends a write command to the adapter. The adapter attempts to interrupt the second computer. The latter, when ready, issues a sense command to the adapter which in response supplies to the second computer, the (write) command from the first (which was stored in the adapter). The second computer generates a read command and the adapter supplies status information to the first. A comparison is made in the adapter to assure that both computers are not executing the same command. Provided they are not, the adapter signals for successive bytes of data from the first computer and transfers them via a buffer to the second computer. When all the data has been transferred, the first computer issues a stop command to the adapter which generates a status signal and then disconnects from both computers whereupon the latter proceed to scan their respective I-O control units independently. If the comparison (see above) had indicated the same command was being executed, an appropriate status signal would be provided to the initiating computer and the adapter would disconnect. A test I/O command can be used to determine the status of the adapter.

    15.
    发明专利
    未知

    公开(公告)号：BR7204117D0

    公开(公告)日：1973-06-14

    申请号：BR411772

    申请日：1972-06-23

    Applicant: IBM

    Inventor： BEAUSOLEIL W

    IPC: G06F11/10 ,  G11C29/00 ,  G06F13/00 ,  H01L19/00

    Abstract: A computer memory, most particularly a monolithic memory, may be constructed of components which contain defective bit cells. During the production process, the monolithic chips are sorted into groups in accordance with the chip sector which contains one or more defective cells. The chips are then mounted on memory cards, with all of the chips having a defect in a given chip sector being mounted on a corresponding card sector. The cards, each of which is produced in a substantially identical manner, are then assembled into a complete memory. The address wiring of the memory is provided in such a manner as to ensure that no given memory word, or defined group of bits within a memory word, contains within it more than one memory cell that is known or suspected to be defective. Means are also provided for deriving from the address of any given memory word the bit location within said word of a defective or suspicious bit. In one embodiment shown herein, the suspect bit is bypassed in favor of a redundant bit provided within the memory system. In another embodiment described herein, the suspect bit is utilized just as if it were a good bit, but, upon detection of an error, the suspect bit will be presumed to be in error.

    16.
    发明专利
    未知

    公开(公告)号：SE341935B

    公开(公告)日：1972-01-17

    申请号：SE636466

    申请日：1966-05-10

    Applicant: IBM

    Inventor： SMITH R ,  BEAUSOLEIL W ,  CLARK W ,  HILL P

    IPC: G06F7/50 ,  G06F12/14 ,  G06F13/12

    Abstract: 1,142,465. Data processors. INTERNATIONAL BUSINESS MACHINES CORP. 2 May, 1966 [12 May, 1965], No. 19173/66. Heading G4A. In a data processing system, access to an address in peripheral storage is permitted or prevented in accordance with the result of a comparison of the address with information developed from a stored catalogue of addresses available to the current programme. A CPU (central processing unit) with associated main core storage can communicate via channels with external devices viz. input/output units and storage units (e.g. disc units). A stored catalogue, in the main storage or an external storage unit, specifies for each data file in an external storage unit, the boundaries of the file (high and low, cylinder and head numbers in the case of a disc unit) and the types of writing and reading access permitted to the associated problem programme. Other problem programmes are denied all access. The control unit of an external storage unit, on being selected for storage access, receives the relevant information from the catalogue byte by byte, the bytes being passed on respective odd counts of a counter in the control unit, from an in - put/output register which initially receives them, to respective further registers in the control unit. The access attempt is terminated and the CPU interrupted and informed of the reason, if the input/output register does not hold zero on any even count, during this. In the absence of this error indication, the cylinder and head numbers of the desired address are received into the input/output register in turn and compared with the boundary bytes in turn, under control of the counter, in the following order (disc unit): cylinder high, cylinder low, head high, head low. The required cylinder and head are selected as soon as their respective comparisons say yes, but if any comparison says no, the access attempt is terminated without further comparisons and the CPU interrupted as before. Termination &c. will also occur if the access is of a non-permitted type, as determined in the control unit, or if the input/output register does not hold zero at certain times before and after the comparisons. Cylinder selection involves finding the difference between the present and desired cylinder numbers, in an adder. A circuit is provided to detect any attempt to set said further registers with more than one set of information from the catalogue. In a modification mentioned, the catalogue supplies two bits specifically allowing or forbidding movement from the current head and cylinder respectively, instead of the boundary data. Conventional arrangements for selection of an external device, including transmission of status back, are described.

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