-
公开(公告)号:AU3713971A
公开(公告)日:1973-06-28
申请号:AU3713971
申请日:1971-12-20
Applicant: IBM
Inventor: BEAUSOLEIL WILLIAM FRANCIS , HO IRVING TZE , PRICER WILBUR DAVID
IPC: G06F12/08 , G11C11/415 , G11C19/00 , G11C15/00 , G06F5/06
Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.
-
公开(公告)号:DE2240433A1
公开(公告)日:1973-03-08
申请号:DE2240433
申请日:1972-08-17
Applicant: IBM
Inventor: BEAUSOLEIL WILLIAM FRANCIS , PHELPS BYRON EUGENE
Abstract: A hierarchical memory for a data processing system which is comprised of a number of different independent storage modules and a main memory backing store. Each data handling element of the system has an independent storage module associated with it as a dedicated buffer. A larger high speed main storage is used as a backing store. Each data handling element presumes that any data it needs is located in its dedicated buffer. If the data is not in the dedicated buffer, the data handling element scans all the other buffers until the desired data is located.
-
公开(公告)号:DK146837B
公开(公告)日:1984-01-16
申请号:DK333470
申请日:1970-06-26
Applicant: IBM
Inventor: BEAUSOLEIL WILLIAM FRANCIS , BROWN PAUL JOSEPH
-
公开(公告)号:DE2359731A1
公开(公告)日:1974-07-04
申请号:DE2359731
申请日:1973-11-30
Applicant: IBM
Inventor: BEAUSOLEIL WILLIAM FRANCIS , HENNET PETER PAUL , MALING KLIM , POWERS NORMAN KENNETH
IPC: G06F11/34 , G06F12/08 , G06F12/0897 , G06F11/00 , G06F13/06
-
公开(公告)号:AU3930572A
公开(公告)日:1973-08-30
申请号:AU3930572
申请日:1972-02-23
Applicant: IBM
Inventor: BEAUSOLEIL WILLIAM FRANCIS , BROWN DAVID TRENT , WALKER ERNEST LEE
Abstract: This specification discloses a bubble domain memory in which data is arranged for immediacy of access in accordance with its last use. The memory comprises a plurality of parallel shift registers in which data can be accessed in parallel. In other words, each of the shift registers contains a bit of a page or word so that by the performance of one shifting operation all of the bits of the page or word can be accessed. Data in each shift register is arranged in its order of last use so that the access position K of a shift register having K bit positions contains the last bit of information used and the position K-1 preceding the access position K in the shift register contains the bit of data used just previously to the data in the access position K and so on. In these shift registers the shift positions are arranged in loops for shifting the data between the positions of the shift register. Two such loops are provided, one of the loops contains all the shift positions so that data in any position in the shift register can be shifted into the access position K of the register for reading or writing. The other loop contains all the positions of the shift register but the access position K. This second loop is for reordering the data in the shift register in order of last use after data has been shifted into the access position K for reading or writing by the first loop.
-
-
公开(公告)号:AU3515271A
公开(公告)日:1973-05-03
申请号:AU3515271
申请日:1971-10-29
Applicant: IBM
Inventor: BEAUSOLEIL WILLIAM FRANCIS , HO IRVING TZE , JEN TEH-SEN , PRICER WILBUR DAVID , WIEDMANN SIEGFRIED KURT
IPC: G11C11/403 , G11C11/406 , G11C11/4067 , G11C11/4094 , H01L23/535 , H01L27/07 , H01L27/102 , G11C11/40
Abstract: This specification discloses a stored charge storage cell for monolithic memories. The cell comprises a device akin to a silicon-controlled rectifier and can be schematically illustrated as an NPN and a PNP transistor connected together in what is commonly called a hook circuit. A fixed potential is applied to the semiconductor zone of the device not commonly used as a terminal for a silicon-controlled rectifier so that the cell is prevented from latching as a silicon-controlled rectifier or hook circuit would normally latch. The charge on the capacitance of collector-base PN junctions of the NPN and PNP transistors is then controlled to store data in the cell.
-
公开(公告)号:GB1152166A
公开(公告)日:1969-05-14
申请号:GB2666167
申请日:1967-06-09
Applicant: IBM
Inventor: BEAUSOLEIL WILLIAM FRANCIS , GARCIA JEAN , GERGAUD FERNAND
Abstract: 1,152,166. Keyboard code generators. INTERNATIONAL BUSINESS MACHINES CORP. 9 June, 1967 [15 June, 1966], No. 26661/67. Heading G4H. [Also in Division H4] A keysender comprises a column of liquid 3 and a switch member 4, each key being arranged, on actuation, to displace the liquid so that member 4 is moved a distance uniquely corresponding to the actuated key. In one embodiment, the liquid is mercury and member 4 is non-conductive. When a key is depressed, a resilient tube 2 is deformed to displace a corresponding volume of liquid, terminals A, B being short-circuited by bridging of contacts 8 while member 4 is moving to the appropriate position between a pair of contacts 1 1 -9 1 , 0. When the key is released, gas under pressure enters chambers 5, 6, and as member 4 returns to the starting position, the continuity of conductor L 1 is interrupted a number of times depending on the key actuated. In another embodiment, the liquid is non-conductive and member 4 is conductive, causing bridging of successive pairs of parallel-connected contacts. Alternatively, member 4 may interrupt a conductive path between a pair of contacts and produce a single pulse of variable duration.
-
公开(公告)号:FR92806E
公开(公告)日:1969-01-03
申请号:FR06007886
申请日:1966-06-21
Applicant: IBM FRANCE
Inventor: BEAUSOLEIL WILLIAM FRANCIS , MELAS CONSTANTIN MICHAEL
Abstract: 1,179,448. Automatic exchange systems. INTERNATIONAL BUSINESS MACHINES CORP. 9 June, 1967 [21 June, 1966], No. 26662/67. Addition to 1,115,520. Heading H4K. The path seeking apparatus of the parent Specification is modified as a result of a more economical expression of the logical functions employed; the logic circuits which examine path co-ordinates, in search of conflict between existing paths and proposed paths, are consequently simplified considerably.
-
公开(公告)号:FR1490670A
公开(公告)日:1967-08-04
申请号:FR06007880
申请日:1966-06-15
Applicant: IBM FRANCE
Inventor: BEAUSOLEIL WILLIAM FRANCIS , GARCIA JEAN , GERGAUD FERNAND
-
-
-
-
-
-
-
-
-