公开(公告)号：PL362792A1

公开(公告)日：2004-11-02

申请号：PL36279201

申请日：2001-01-31

Applicant: IBM

Inventor： BIRAN GIORA ,  SOSTHEIM TAL

IPC: G06F13/00 ,  G06F13/40 ,  H04L12/26 ,  H04L12/56

Abstract: Apparatus, methods and systems for controlling data flow between data processing systems. In an example embodiment, the apparatus includes descriptor logic for generating a plurality of descriptors including a frame descriptor defining a data packet to be communicated between a location in the memory and a data processing system, and a pointer descriptor identifying the location in the memory. The apparatus also includes a descriptor table for storing descriptors generated by the descriptor logic for access by the data processing systems.

公开(公告)号：DE112018004142T5

公开(公告)日：2020-04-23

申请号：DE112018004142

申请日：2018-08-02

Applicant: IBM

Inventor： BIRAN GIORA ,  LOBO PREETHAM ,  WEBEL TOBIAS ,  BUYUKTOSUNOGLU ALPER ,  VEZYRTZIS CHRISTOS ,  BERTRAN MONFORT RAMON ,  CHUANG PIERCE I-JEN ,  RESTLE PHILLIP JOHN ,  BOSE PRADIP

IPC: G06F1/30 ,  G06F1/28 ,  G06F1/32 ,  G06F9/38

Abstract: Es werden Techniken bereitgestellt, die eine Verringerung und/oder Minderung eines Spannungseinbruchs in einem Prozessorkern ermöglichen. In einem Beispiel kann ein System einen Hauptspeicher, in dem durch einen Computer ausführbare Komponenten gespeichert sind, und einen Prozessor aufweisen, der diese ausführt. Die durch einen Computer ausführbaren Komponenten können eine Beobachtungskomponente aufweisen, die ein oder mehrere Ereignisse in einer ersten Stufe einer Prozessor-Pipeline erkennt. Bei einem Ereignis aus dem einen oder den mehreren Ereignissen kann es sich um ein definiertes Ereignis handeln, das als einen Pegel an Leistung, die während einer zweiten Stufe der Prozessor-Pipeline verbraucht wird, erhöhend ermittelt wird. Die durch einen Computer ausführbaren Komponenten können auch eine Anweisungskomponente, die vor der Erhöhung des Pegels der Leistung, die während der zweiten Stufe der Prozessor-Pipeline verbraucht wird, eine Gegenmaßnahme zur Minderung eines Spannungseinbruchs anwendet, und eine Rückkopplungskomponente aufweisen, die der Anweisungskomponente eine Benachrichtigung bereitstellt, die einen Erfolg oder einen Misserfolg eines Ergebnisses der Gegenmaßnahme zur Minderung eines Spannungseinbruchs anzeigt.

公开(公告)号：DE602004027543D1

公开(公告)日：2010-07-15

申请号：DE602004027543

申请日：2004-12-06

Applicant: IBM

Inventor： MAKHERVAKS VADIM ,  MACHULSKY ZORIK ,  BIRAN GIORA ,  SHALEV LEAH

IPC: G06F15/16 ,  H04L29/06

公开(公告)号：HU0302843A2

公开(公告)日：2003-12-29

申请号：HU0302843

申请日：2001-01-31

Applicant: IBM

Inventor： BIRAN GIORA ,  MACHULSKY GEORGY ,  SCHILLER CLAUDIU ,  SOSTHEIM TAL

IPC: G06F3/00 ,  G06F13/24

Abstract: Methods, systems and apparatus for transferring interrupts from a peripheral device to a host computer system is described. In an example embodiment, an apparatus comprises a buffer for storing indications of interrupts generated by the peripheral device. In response to a preset condition being met, a controller generates a control data block having a payload portion, moves the contents of the buffer to the payload portion of the control data block, and sends the control data block to the host computer system.

公开(公告)号：CA2548966A1

公开(公告)日：2005-07-07

申请号：CA2548966

申请日：2004-12-06

Applicant: IBM

Inventor： MAKHER-VAKS VADIM ,  MACHULSKY ZORIK ,  BIRAN GIORA ,  SHALEV LEAH

IPC: G06F15/16 ,  H04L29/06

Abstract: An RNIC implementation that performs direct data placement to memory where a ll segments of a particular connection are aligned, or moves data through reassembly buffers where all segments of a particular connection are non- aligned. The type of connection that cuts-through without accessing the reassembly buffers is referred to as a "Fast" connection because it is highl y likely to be aligned, while the other type is referred to as a "Slow" connection. When a consumer establishes a connection, it specifies a connection type (S2). The connection type can change from Fast to Slow and back. The invention reduces memory bandwidth, latency, error recovery using TCP retransmit and provides for a "graceful recovery" from an empty receive queue. The implementation also may conduct CRC validation (S11, S6) for a majority of inbound DDP segments in the Fast connection before sending a TCP acknowledgement (Ack) confirming segment reception.

公开(公告)号：CZ20032079A3

公开(公告)日：2003-12-17

申请号：CZ20032079

申请日：2001-01-31

Applicant: IBM

Inventor： BIRAN GIORA ,  SOSTHEIM TAL ,  MACHULSKY GEORGY ,  SCHILLER CLAUDIU

IPC: G06F3/00 ,  G06F13/24

Abstract: Methods, systems and apparatus for transferring interrupts from a peripheral device to a host computer system is described. In an example embodiment, an apparatus comprises a buffer for storing indications of interrupts generated by the peripheral device. In response to a preset condition being met, a controller generates a control data block having a payload portion, moves the contents of the buffer to the payload portion of the control data block, and sends the control data block to the host computer system.

公开(公告)号：AT470187T

公开(公告)日：2010-06-15

申请号：AT04813127

申请日：2004-12-06

Applicant: IBM

Inventor： MAKHERVAKS VADIM ,  MACHULSKY ZORIK ,  BIRAN GIORA ,  SHALEV LEAH

IPC: G06F15/16 ,  H04L29/06

Abstract: An RNIC implementation that performs direct data placement to memory where all segments of a particular connection are aligned, or moves data through reassembly buffers where all segments of a particular connection are non-aligned. The type of connection that cuts-through without accessing the reassembly buffers is referred to as a "Fast" connection because it is highly likely to be aligned, while the other type is referred to as a "Slow" connection. When a consumer establishes a connection, it specifies a connection type. The connection type can change from Fast to Slow and back. The invention reduces memory bandwidth, latency, error recovery using TCP retransmit and provides for a "graceful recovery" from an empty receive queue. The implementation also may conduct CRC validation for a majority of inbound DDP segments in the Fast connection before sending a TCP acknowledgement (Ack) confirming segment reception.

公开(公告)号：CA2548966C

公开(公告)日：2010-06-01

申请号：CA2548966

申请日：2004-12-06

Applicant: IBM

Inventor： MAKHER-VAKS VADIM ,  MACHULSKY ZORIK ,  BIRAN GIORA ,  SHALEV LEAH

IPC: H04L29/08 ,  G06F15/16 ,  H04L29/06

Abstract: An RNIC implementation that performs direct data placement to memory where all segments of a particular connection are aligned, or moves data through reassembly buffers where all segments of a particular connection are non-aligned. The type of connection that cuts-through without accessing the reassembly buffers is referred to as a "Fast" connection because it is highly likely to be aligned, while the other type is referred to as a "Slow" connection. When a consumer establishes a connection, it specifies a connection type (S2). The connection type can change from Fast to Slow and back. The invention reduces memory bandwidth, latency, error recovery using TCP retransmit and provides for a "graceful recovery" from an empty receive queue. The implementation also may conduct CRC validation (S11, S6) for a majority of inbound DDP segments in the Fast connection before sending a TCP acknowledgement (Ack) confirming segment reception.

公开(公告)号：PL363432A1

公开(公告)日：2004-11-15

申请号：PL36343201

申请日：2001-01-31

Applicant: IBM

Inventor： BIRAN GIORA ,  MACHULSKY GEORGY ,  SCHILLER CLAUDIU ,  SOSTHEIM TAL

IPC: G06F3/00 ,  G06F13/24

Abstract: Methods, systems and apparatus for transferring interrupts from a peripheral device to a host computer system is described. In an example embodiment, an apparatus comprises a buffer for storing indications of interrupts generated by the peripheral device. In response to a preset condition being met, a controller generates a control data block having a payload portion, moves the contents of the buffer to the payload portion of the control data block, and sends the control data block to the host computer system.

公开(公告)号：CA2432387A1

公开(公告)日：2002-08-08

申请号：CA2432387

申请日：2001-01-31

Applicant: IBM

Inventor： BIRAN GIORA ,  SOSTHEIM TAL

IPC: G06F13/00 ,  G06F13/40 ,  H04L12/26 ,  H04L12/56

Abstract: Apparatus is described for controlling flow of data between first and second data processing systems via a memory. The apparatus comprises descriptor log ic for generating a plurality of descriptors including a frame descriptor defining a data packet to be communicated between a location in the memory a nd the second data processing system, and a pointer descriptor identifying the location in the memory. The apparatus also comprises a descriptor table for storing the descriptors generated by the descriptor logic for access by the first and second data processing systems.