公开(公告)号：DE69809224D1

公开(公告)日：2002-12-12

申请号：DE69809224

申请日：1998-08-28

Applicant: IBM

Inventor： BLANC ALAIN ,  ORENGO GERARD ,  PORET MICHEL

IPC: H03M9/00 ,  H04L49/111 ,  H04Q11/04 ,  H04L12/56

Abstract: A switching apparatus comprising a centralized Switch Core (10) and at least one SCAL element for the attachment of Protocol Adapters. The Switch Core and the SCAL communicate to each other via n parallel serial links with each one transmitting a Logical Unit. Each SCAL comprises both the receive and the transmit part at least one input for receiving cells from said Protocol Adapter; a set of n FIFO queues (21-25) for storing the cells into n parallel busses; and a set of n RAM storages, with each RAM being associated with one Logical Unit. First multiplexing means (31) receive the contents of the parallel busses for performing simultaneously n WRITE operations into the n RAM storages under control of a first set of n tables ( 36-39). Second multiplexing (41) means are provided for making READ operations from said n RAM storages under control of a second set of n tables ( 46-49). By appropriate arrangement of the two sets of tables, which are chosen complementary, the cells which are conveyed through the first multiplexing means, the RAMs and the second multiplexing means are subject to a cell rearrangement enabling to introduce at least one bitmap field, thereby producing said four Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage (50-80), one particular byte is accidentally stored into one RAM available for a Write operation by means of said first set of tables, thereby causing an alteration to the normal association between said n RAMs and said n Logical Units which is then restablished by said second set of tables.

公开(公告)号：DE69114129T2

公开(公告)日：1996-06-13

申请号：DE69114129

申请日：1991-07-17

Applicant: IBM

Inventor： ABBIATE JEAN-CLAUDE ,  BLANC ALAIN ,  JEANNIOT PATRICK ,  ORENGO GERARD ,  RICHTER GERARD

IPC: H04B14/06 ,  H03H17/06

Abstract: A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock into a train of PCM samples which includes counting means (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storing means (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and means (327, 337, 347) driven by the sigma-delta clock for incrementing the storing means with the incrementation parameter DELTA(n). At last, the decimation filter includes computing means (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storing means and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3xN input sigma-delta samples according to the formula: Since the coefficients C(n) are directly and on-line computed with the reception of the sigma-delta pulses, the decimation filter can operate for any value of the decimation parameter without requiring the use of substantial digital processing resources. The decimation filter can be used for a wide variety of different applications requiring different decimation factors.

公开(公告)号：DE69114129D1

公开(公告)日：1995-11-30

申请号：DE69114129

申请日：1991-07-17

Applicant: IBM

Inventor： ABBIATE JEAN-CLAUDE ,  BLANC ALAIN ,  JEANNIOT PATRICK ,  ORENGO GERARD ,  RICHTER GERARD

IPC: H04B14/06 ,  H03H17/06

Abstract: A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock into a train of PCM samples which includes counting means (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storing means (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and means (327, 337, 347) driven by the sigma-delta clock for incrementing the storing means with the incrementation parameter DELTA(n). At last, the decimation filter includes computing means (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storing means and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3xN input sigma-delta samples according to the formula: Since the coefficients C(n) are directly and on-line computed with the reception of the sigma-delta pulses, the decimation filter can operate for any value of the decimation parameter without requiring the use of substantial digital processing resources. The decimation filter can be used for a wide variety of different applications requiring different decimation factors.

公开(公告)号：DE3783915D1

公开(公告)日：1993-03-11

申请号：DE3783915

申请日：1987-10-19

Applicant: IBM

Inventor： ABBIATE JEAN-CLAUDE ,  BLANC ALAIN ,  JEANNIOT PATRICK ,  LALLEMAND ERIC

IPC: H04L7/033 ,  H04L7/02

Abstract: An eye opening time measuring block includes a counter controlled by an analog squared signal derived from the data flow on the line. A division by two is effected to determine the best sampling time. A counter is set running in response to the first transition of the multilevel digital signal and is halted at a second transition of the signal. The divide-by-two circuit divides the interval determined between the first and second transitions of the signal by two. The result is applied to a phase locked oscillator (124) which generates a sampling clock with the middle of the eye of the analog squared wave signal.

公开(公告)号：DE60135234D1

公开(公告)日：2008-09-18

申请号：DE60135234

申请日：2001-09-06

Applicant: IBM

Inventor： WIND DANIEL ,  ROMAN THIERRY ,  BLANC ALAIN ,  BREZZO BERNARD ,  GALLEZOT RENE ,  LE MAUT FRANCOIS

IPC: H04L12/18 ,  H04L49/111

Abstract: A data switch is provided which routes fixed-size data packets from input ports to output ports, using shared memory which holds a copy of each packet in buffers. Output ports have a queue which contains pointers to buffers holding packets bound for that port. The number of shared memory buffers holding packets is compared to the number of buffer pointers in the output queues. In this way, a Multicast Index (MCI), a metric of the level of multicast traffic, is derived. The switch includes a Switch Core Adaptation Layer (SCAL) which has a multicast input queue. Because traffic is handled based on priority class P, a multicast threshold MCT(P), associated with the multicast input queue, is established per priority. While receiving traffic, the MCI is updated and, for each priority class in each SCAL, the MCI is compared to the MCT(P) to determine whether corresponding multicast traffic must be held.

公开(公告)号：AT404001T

公开(公告)日：2008-08-15

申请号：AT01976198

申请日：2001-09-06

Applicant: IBM

Inventor： WIND DANIEL ,  ROMAN THIERRY ,  BLANC ALAIN ,  BREZZO BERNARD ,  GALLEZOT RENE ,  LE MAUT FRANCOIS

IPC: H04L12/18 ,  H04L49/111

Abstract: A data switch is provided which routes fixed-size data packets from input ports to output ports, using shared memory which holds a copy of each packet in buffers. Output ports have a queue which contains pointers to buffers holding packets bound for that port. The number of shared memory buffers holding packets is compared to the number of buffer pointers in the output queues. In this way, a Multicast Index (MCI), a metric of the level of multicast traffic, is derived. The switch includes a Switch Core Adaptation Layer (SCAL) which has a multicast input queue. Because traffic is handled based on priority class P, a multicast threshold MCT(P), associated with the multicast input queue, is established per priority. While receiving traffic, the MCI is updated and, for each priority class in each SCAL, the MCI is compared to the MCT(P) to determine whether corresponding multicast traffic must be held.

公开(公告)号：DE69826640T2

公开(公告)日：2005-10-06

申请号：DE69826640

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  ROBBE JEAN-CLAUDE ,  GOHL SYLVIE ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching architecture comprising a first and a second Switch Fabrics (10, 20) including a switch core (15, 25) located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of the switch core. The Port Adapters (30; 31) are distributed at different physical areas and each one is connected to the first and second Switch Fabric via a particular SCAL element so that each Switch core (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch core. There are arranged means (15, 100) for assigning a particular Switch core to any Port adapter for the normal traffic of cells and for reserving the other switch core to Backup or maintenance traffic situations. To achieve this each switch core is fitted with a masking mechanism which uses the value loaded into a Mask register for altering the bitmap value which is normally used inside the switch core for controlling the routing process. Since the Mask registers in the two switch cores are loaded with complementary values, this permits a perfect distribution of the cells via one and only one SCAL Xmit element towards any Port Adapter. Preferably the Mask mechanism can be controlled by a special control field located into the cell, or when maintenance of backup conditions are planned.

公开(公告)号：DE69817159T2

公开(公告)日：2004-05-06

申请号：DE69817159

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching system (15 or 25) receiving data cells from a set of n input ports and to be routed to one or more output ports in accordance with the contents of a bitmap value introduced in the cell at the entrance of said module, said module comprising a shared buffer for storing the cells which are to be routed. The systems further comprises a mask mechanism with a mask register for altering the value of the bitmap before it is used for controlling the routing process for either transporting the considered cell to the output port or discarding the latter. Two switching systems are combined in a first and a second Switch Fabrics (10, 20) in order to respectively form a first and second switch cores, located in a centralized building and a set of Switch Core Access Layer (S.C.A.L.) elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of one of said switching system. A set of Port Adapters (30; 31) are distributed at different physical areas and are connected to said first and second Switch Fabrics via a particular SCAL element so that each Switching system (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch cores. The mask achieves the distribution of the first and second switching systems between the different attached Port adapters, thus providing a load balancing between the two switching systems permitting to associate their individual buffering resources.

公开(公告)号：DE69023485D1

公开(公告)日：1995-12-14

申请号：DE69023485

申请日：1990-05-15

Applicant: IBM

Inventor： BLANC ALAIN

IPC: G06F13/00 ,  G06F13/38 ,  H04J3/06 ,  H04L7/08

公开(公告)号：DE3575829D1

公开(公告)日：1990-03-08

申请号：DE3575829

申请日：1985-10-30

Applicant: IBM

Inventor： BLANC ALAIN ,  JEANNIOT PATRICK ,  SPALMACIN-ROMA SYLVIE

IPC: H04Q11/04 ,  G06F9/48 ,  G06F13/22 ,  H04B1/66 ,  H04J3/06 ,  H04M1/253

Abstract: The system is made to concentrate n voice signals over a same high speed channel using a single Unit Processor. The data transfers between the Unit Processor and a set of Signal Processors are managed by a counter loaded by the Unit Processor with a predetermined value selected according to the system architecture. The counter is made of two parts serially connected , the first one made for sequentially providing an interrupt request to the Unit Processor and the second one driving a decoder providing signals for serially scanning the set of signal processors and providing time slots for data transfers between Unit Processor and Signal Processors.