公开(公告)号：DE69737676T2

公开(公告)日：2008-01-10

申请号：DE69737676

申请日：1997-08-19

Applicant: IBM

Inventor： BLANC ALAIN ,  SAUREL ALAIN ,  BREZZO BERNARD ,  PORET MICHEL

IPC: H04L49/111 ,  H04Q11/04

Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.

公开(公告)号：DE60135234D1

公开(公告)日：2008-09-18

申请号：DE60135234

申请日：2001-09-06

Applicant: IBM

Inventor： WIND DANIEL ,  ROMAN THIERRY ,  BLANC ALAIN ,  BREZZO BERNARD ,  GALLEZOT RENE ,  LE MAUT FRANCOIS

IPC: H04L12/18 ,  H04L49/111

Abstract: A data switch is provided which routes fixed-size data packets from input ports to output ports, using shared memory which holds a copy of each packet in buffers. Output ports have a queue which contains pointers to buffers holding packets bound for that port. The number of shared memory buffers holding packets is compared to the number of buffer pointers in the output queues. In this way, a Multicast Index (MCI), a metric of the level of multicast traffic, is derived. The switch includes a Switch Core Adaptation Layer (SCAL) which has a multicast input queue. Because traffic is handled based on priority class P, a multicast threshold MCT(P), associated with the multicast input queue, is established per priority. While receiving traffic, the MCI is updated and, for each priority class in each SCAL, the MCI is compared to the MCT(P) to determine whether corresponding multicast traffic must be held.

公开(公告)号：AT404001T

公开(公告)日：2008-08-15

申请号：AT01976198

申请日：2001-09-06

Applicant: IBM

Inventor： WIND DANIEL ,  ROMAN THIERRY ,  BLANC ALAIN ,  BREZZO BERNARD ,  GALLEZOT RENE ,  LE MAUT FRANCOIS

IPC: H04L12/18 ,  H04L49/111

Abstract: A data switch is provided which routes fixed-size data packets from input ports to output ports, using shared memory which holds a copy of each packet in buffers. Output ports have a queue which contains pointers to buffers holding packets bound for that port. The number of shared memory buffers holding packets is compared to the number of buffer pointers in the output queues. In this way, a Multicast Index (MCI), a metric of the level of multicast traffic, is derived. The switch includes a Switch Core Adaptation Layer (SCAL) which has a multicast input queue. Because traffic is handled based on priority class P, a multicast threshold MCT(P), associated with the multicast input queue, is established per priority. While receiving traffic, the MCI is updated and, for each priority class in each SCAL, the MCI is compared to the MCT(P) to determine whether corresponding multicast traffic must be held.

公开(公告)号：DE69826640T2

公开(公告)日：2005-10-06

申请号：DE69826640

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  ROBBE JEAN-CLAUDE ,  GOHL SYLVIE ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching architecture comprising a first and a second Switch Fabrics (10, 20) including a switch core (15, 25) located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of the switch core. The Port Adapters (30; 31) are distributed at different physical areas and each one is connected to the first and second Switch Fabric via a particular SCAL element so that each Switch core (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch core. There are arranged means (15, 100) for assigning a particular Switch core to any Port adapter for the normal traffic of cells and for reserving the other switch core to Backup or maintenance traffic situations. To achieve this each switch core is fitted with a masking mechanism which uses the value loaded into a Mask register for altering the bitmap value which is normally used inside the switch core for controlling the routing process. Since the Mask registers in the two switch cores are loaded with complementary values, this permits a perfect distribution of the cells via one and only one SCAL Xmit element towards any Port Adapter. Preferably the Mask mechanism can be controlled by a special control field located into the cell, or when maintenance of backup conditions are planned.

公开(公告)号：DE69817159T2

公开(公告)日：2004-05-06

申请号：DE69817159

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching system (15 or 25) receiving data cells from a set of n input ports and to be routed to one or more output ports in accordance with the contents of a bitmap value introduced in the cell at the entrance of said module, said module comprising a shared buffer for storing the cells which are to be routed. The systems further comprises a mask mechanism with a mask register for altering the value of the bitmap before it is used for controlling the routing process for either transporting the considered cell to the output port or discarding the latter. Two switching systems are combined in a first and a second Switch Fabrics (10, 20) in order to respectively form a first and second switch cores, located in a centralized building and a set of Switch Core Access Layer (S.C.A.L.) elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of one of said switching system. A set of Port Adapters (30; 31) are distributed at different physical areas and are connected to said first and second Switch Fabrics via a particular SCAL element so that each Switching system (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch cores. The mask achieves the distribution of the first and second switching systems between the different attached Port adapters, thus providing a load balancing between the two switching systems permitting to associate their individual buffering resources.

公开(公告)号：AU558173B2

公开(公告)日：1987-01-22

申请号：AU8979282

申请日：1982-10-26

Applicant: IBM

Inventor： BREZZO BERNARD ,  CALVIGNAC JEAN ,  MASCLET ANDRE ,  SANCHE JEAN-PIERRE

IPC: H04L69/14 ,  G06F13/00 ,  G06F13/38 ,  G06F3/04 ,  H04L11/20

Abstract: A line scanning device which operates under the control of a microprocessor connected to a control memory in which a memory location area is assigned to each line is provided for a line adapter in a communication controller for receiving or sending message bits in series from or to terminals connected to the lines using any protocols. It comprises a first store which includes a first and a second memories, an area being assigned to each line in each of the memories which can be read and written in the same time and a second store which includes a single memory in which a storage location area is assigned to each line. These stores are addressed by a control and address unit which includes first and second address counters under the control of an elementary time counter, the first counter outputting the address information relating to the first store during time t provided for scanning a line, and the second counter outputting the address information relative to the second store during time nt, n being at least equal to 4, and control circuitry receiving said address information and the elementary time information for providing at the outputs of the control and address unit, memory address and read/write control information at times selected during the scanning period and sequentially, the addresses of the present lines which are scanned.

公开(公告)号：DE69737676D1

公开(公告)日：2007-06-14

申请号：DE69737676

申请日：1997-08-19

Applicant: IBM

Inventor： BLANC ALAIN ,  SAUREL ALAIN ,  BREZZO BERNARD ,  PORET MICHEL

IPC: H04L49/111 ,  H04Q11/04

Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.

公开(公告)号：DE69819129T2

公开(公告)日：2004-07-29

申请号：DE69819129

申请日：1998-10-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  DEBORD PIERRE ,  WIDMER ALBERT

IPC: H04J3/00 ,  H04L12/54 ,  H04L25/49 ,  H04L49/111 ,  H04L12/56 ,  H04Q11/04

Abstract: A flow control process for a switching architecture having a central switch core with associated distributed Switch Core Access Layers communicating with the core by means of serial data communication links. The serial links carry data flows that are coded in accordance with the 8B/10B coding, where two among the three comma characters are used for creating an additional specialized flow control channel. When the cells are idle or empty, the nature of the comma character that appears at the beginning of the cell provides the appropriate flow control bit information. For instance, should the K.28.5 character be detected, the receiving entity (either the switching structure or a distributed SCAL element) decodes the character as positive flow control information, corresponding to a request to reduce the incoming data flow. Also, should the K.28.1 character be decoded, then the receiving entity decodes this as information according to which no reduction in the data flow is requested. When the incoming flow provides data cells, the invention uses a predetermined bit within the data cell, generally that immediately following the beginning of the cell, in order to carry the flow control information.

公开(公告)号：DE69819129D1

公开(公告)日：2003-11-27

申请号：DE69819129

申请日：1998-10-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  DEBORD PIERRE ,  WIDMER ALBERT

IPC: H04J3/00 ,  H04L12/54 ,  H04L25/49 ,  H04L49/111 ,  H04L12/56 ,  H04Q11/04

Abstract: A flow control process for a switching architecture having a central switch core with associated distributed Switch Core Access Layers communicating with the core by means of serial data communication links. The serial links carry data flows that are coded in accordance with the 8B/10B coding, where two among the three comma characters are used for creating an additional specialized flow control channel. When the cells are idle or empty, the nature of the comma character that appears at the beginning of the cell provides the appropriate flow control bit information. For instance, should the K.28.5 character be detected, the receiving entity (either the switching structure or a distributed SCAL element) decodes the character as positive flow control information, corresponding to a request to reduce the incoming data flow. Also, should the K.28.1 character be decoded, then the receiving entity decodes this as information according to which no reduction in the data flow is requested. When the incoming flow provides data cells, the invention uses a predetermined bit within the data cell, generally that immediately following the beginning of the cell, in order to carry the flow control information.

公开(公告)号：CA2422221A1

公开(公告)日：2002-03-21

申请号：CA2422221

申请日：2001-09-06

Applicant: IBM

Inventor： WIND DANIEL ,  ROMAN THIERRY ,  BLANC ALAIN ,  GALLEZOT RENE ,  LE MAUT FRANCOIS ,  BREZZO BERNARD

IPC: H04L12/18 ,  H04L49/111 ,  H04L12/56

Abstract: The invention allows to assess a level of multicast traffic in a data switch of the kind devised to steer fixed-size data packets, from input to output ports, through a shared memory which temporarily holds a single copy of them in buffers. Output ports are each equipped with an output port queue which contains pointers to those of the buffers holding data packets due to leave the data switch through them. Then, the invention assumes that the total number of shared-memory buffers currently holding a data packet is counted a nd compared to the total number of buffer pointers found in the output queues. Hence, a metric of the level of multicast traffic is derived resulting in th e calculation of a MultiCast Index (MCI). The invention further assumes that data switch is used together with a Switch Core Adaptation Layer (SCAL) whic h includes a multicast input queue. Because traffic is handled on the basis of a set of priority classes a multicast threshold MCT(P), associated to the multicast input queue, per priority, is set or updated. Therefore, while receiving incoming data traffic, MCI is kept calculated and, for each priori ty class (P), in each SCAL, MCI is compared to MCT(P) to determine whether corresponding multicast traffic must be held or not. The invention helps preventing traffic congestion in communications networks, using fixed-size data packet switches, that would otherwise occur when a high level of multicast and broadcast traffic has to be supported at network nodes.