公开(公告)号：GB2577845A

公开(公告)日：2020-04-08

申请号：GB202000470

申请日：2018-06-14

Applicant: IBM

Inventor： CHRISTIAN ZOELLIN ,  CHRISTIAN JACOBI ,  CHUNG-LUNG K SHUM ,  MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  AARON TSAI

IPC: G06F12/0815

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

公开(公告)号：GB2576288A

公开(公告)日：2020-02-12

申请号：GB201917044

申请日：2018-05-21

Applicant: IBM

Inventor： JANG-SOO LEE ,  CHRISTIAN JACOBI ,  CHRISTIAN ZOELLIN ,  DAVID LEE ,  JANE BARTIK ,  ANTHONY SAPORITO

IPC: G06F9/38

Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.