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    System, device, and method of providing counter for scaling operating frequency of microprocessor
    1.
    发明专利
    System, device, and method of providing counter for scaling operating frequency of microprocessor 有权
    提供微处理器操作频率的计数器的系统，设备和方法

    公开(公告)号：JP2007200303A

    公开(公告)日：2007-08-09

    申请号：JP2006351591

    申请日：2006-12-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： DR CEDRIC LICHTENAU ,  MARTIN RECKTENWALD ,  SCHMIDT ANDREAS ,  PFLUEGER THOMAS ,  KUENZER JENS ,  ROLF HILGENDORF B

    IPC: G06F1/04 ,  G06F1/08

    CPC classification number: G06F1/14 ,  G04F10/04 ,  H03L7/06

    Abstract: PROBLEM TO BE SOLVED: To provide a system, a device, and a method of providing an accurate time-based counter for scaling an operating frequency of a microprocessor. SOLUTION: This system, this device, and this method make use of a time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of a clock generation circuit of the microprocessor and is used to be fed to external and internal timebase logic and a timebase accumulator counter. The timebase accumulator counter accumulates tick events from the timebase logic between two core clocks. The accumulated value is transferred to a core clock domain on every clock edge of a scalable clock, and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种系统，设备和提供用于缩放微处理器的工作频率的精确的基于时间的计数器的方法。 解决方案：该系统，该装置和该方法利用基于时间的计数器电路配置，其中固定频率时钟源自微处理器的时钟产生电路的PLL并且被用于馈送到 外部和内部时基逻辑和时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器被复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。 版权所有（C）2007，JPO＆INPIT

    Reducing cache transfer overhead in a system
    3.
    发明专利
    Reducing cache transfer overhead in a system 未知

    公开(公告)号：GB2577845B

    公开(公告)日：2020-09-23

    申请号：GB202000470

    申请日：2018-06-14

    Applicant: IBM

    Inventor： CHRISTIAN ZOELLIN ,  CHRISTIAN JACOBI ,  CHUNG-LUNG K SHUM ,  MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  AARON TSAI

    IPC: G06F12/0815

    Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

    Translation support for a virtual cache
    4.
    发明专利
    Translation support for a virtual cache 未知

    公开(公告)号：GB2577023B

    公开(公告)日：2020-08-05

    申请号：GB202000046

    申请日：2018-06-14

    Applicant: IBM

    Inventor： MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  CHISTIAN JACOBI ,  AARON TSAI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS ,  ULRICH MAYER

    IPC: G06F12/0842 ,  G06F12/0808 ,  G06F12/10

    Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

    Reducing cache transfer overhead in a system
    5.
    发明专利
    Reducing cache transfer overhead in a system 未知

    公开(公告)号：GB2577845A

    公开(公告)日：2020-04-08

    申请号：GB202000470

    申请日：2018-06-14

    Applicant: IBM

    Inventor： CHRISTIAN ZOELLIN ,  CHRISTIAN JACOBI ,  CHUNG-LUNG K SHUM ,  MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  AARON TSAI

    IPC: G06F12/0815

    Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

    Sharing virtual and real translations in a virtual cache
    8.
    发明专利
    Sharing virtual and real translations in a virtual cache 未知

    公开(公告)号：GB2577468A

    公开(公告)日：2020-03-25

    申请号：GB202000448

    申请日：2018-06-14

    Applicant: IBM

    Inventor： MARTIN RECKTENWALD ,  CHRISTIAN JACOBI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS

    IPC: G06F12/0875 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/1027

    Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

    Translation support for a virtual cache
    9.
    发明专利
    Translation support for a virtual cache 未知

    公开(公告)号：GB2577023A

    公开(公告)日：2020-03-11

    申请号：GB202000046

    申请日：2018-06-14

    Applicant: IBM

    Inventor： MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  CHISTIAN JACOBI ,  AARON TSAI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS ,  ULRICH MAYER

    IPC: G06F12/0842 ,  G06F12/0808 ,  G06F12/10

    Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

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