公开(公告)号：DE69920830D1

公开(公告)日：2004-11-11

申请号：DE69920830

申请日：1999-06-19

Applicant: IBM

Inventor： CLEMEN RAINER ,  MIELICH HARALD ,  PILLE JUERGEN

IPC: G11C7/06 ,  G11C11/419 ,  G11C29/12 ,  G11C7/00 ,  G11C29/00

Abstract: For high-speed single-ended sensing of the signal from a (multi-port) SRAM cell, a configurable half-latch with 2 PFET feedback pathes is proposed, which can be set up either as a bleeder device in the system mode or as keeper devices in the test modes, controlled by a DC signal (TEST). The bleeder and keepers are attached to the bit line and gated by a small ratioed inverter serving as sense amplifier. In case of system mode, a low control signal is applied to the source of the bleeder to limit the bit line up-level to a threshold below the supply voltage Vdd. Thus, discharging the bit line when reading a '0' is fast. Reading a '1' is also fast by skewing the inverter to a PFET/NFET ratio below 1. For chip testing, the control signal is set high to enable the keepers which restore the bit line close to the supply voltage, even when large subthreshold currents try to discharge it via the unselected cells. This turns off the PFET of the inverter, thereby minimizing the DC current. The new approach improves the access time by about 10%, since no speed must be sacrificed for low-power operation during reliability tests at high voltage (1.5x to 2x Vdd) and temperature.

公开(公告)号：DE69230366T2

公开(公告)日：2000-06-08

申请号：DE69230366

申请日：1992-02-06

Applicant: IBM

Inventor： CLEMEN RAINER ,  GETZLAFF KLAUS JOERG ING GRAD

IPC: G11C11/41 ,  G11C8/16 ,  G11C8/00

Abstract: A fast write-thru scheme is proposed for use in a multi-port static random access memory. This is achieved by operating the read and write ports of the SRAM circuitry in two separate but interleaved stages. In a first stage, a write path is set up comprising a write address decoder (244), an AND gate (245) connected to a clock signal (CE) and the write port (260) and latch (290) of a memory cell (200). In the second stage, a read path is set up comprising a read address decoder (254), a latch (290), read port (270-274) and a data out buffer (225). To minimise the write-thru access time, the asynchronous read path controlled by the read address is interleaved with the write path triggered by a write clock (CE), so that the read address is delayed with respect to the clock and the write addresses. Thus the write-thru access time becomes independent from the write time needed for overwriting the multi-port SRAM cell and equal to the read address access time (Taa) achieved in a fully static or asynchronous read operation. The proposed timing scheme is particularly suited for structured and expandable multi-port SRAMs embedded on CMOS VLSI logic chips.

公开(公告)号：DE69230366D1

公开(公告)日：2000-01-05

申请号：DE69230366

申请日：1992-02-06

Applicant: IBM

Inventor： CLEMEN RAINER ,  GETZLAFF KLAUS JOERG ING GRAD

IPC: G11C11/41 ,  G11C8/16 ,  G11C8/00

Abstract: A fast write-thru scheme is proposed for use in a multi-port static random access memory. This is achieved by operating the read and write ports of the SRAM circuitry in two separate but interleaved stages. In a first stage, a write path is set up comprising a write address decoder (244), an AND gate (245) connected to a clock signal (CE) and the write port (260) and latch (290) of a memory cell (200). In the second stage, a read path is set up comprising a read address decoder (254), a latch (290), read port (270-274) and a data out buffer (225). To minimise the write-thru access time, the asynchronous read path controlled by the read address is interleaved with the write path triggered by a write clock (CE), so that the read address is delayed with respect to the clock and the write addresses. Thus the write-thru access time becomes independent from the write time needed for overwriting the multi-port SRAM cell and equal to the read address access time (Taa) achieved in a fully static or asynchronous read operation. The proposed timing scheme is particularly suited for structured and expandable multi-port SRAMs embedded on CMOS VLSI logic chips.

公开(公告)号：DE3069456D1

公开(公告)日：1984-11-22

申请号：DE3069456

申请日：1980-07-24

Applicant: IBM

Inventor： CLEMEN RAINER ,  FISCHER WALTER ,  HAUG WERNER

IPC: H03K5/00 ,  H03K5/02 ,  H03K19/0185 ,  H03K19/094