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    PROCESSING OF COMPACTED DATA
    11.
    发明专利
    PROCESSING OF COMPACTED DATA 未知

    公开(公告)号：CA1030658A

    公开(公告)日：1978-05-02

    申请号：CA135902

    申请日：1972-03-01

    Applicant: IBM

    Inventor： COCKE JOHN ,  MOMMENS JACQUES H ,  RAVIV JOSEF

    IPC: H03M7/40 ,  H03M7/42 ,  H03K13/24

    Abstract: This data processing technique utilizes compacted data in the form of variable-length codes having length-representing prefix portions which themselves are variable-length encoded. The relatively small amount of storage needed when such a code format is used enables data to be conveniently encoded and handled as groups of characters rather than as single characters. The variable-length prefixes are decoded by a small, fast, search-only type of associative memory which furnishes a match-indicating signal as an address to another memory having conventional storage elements. The output of the latter may contain a base address in still another memory of conventional type and an indication of how many bits remain in the current variable-length code word. These remaining bits furnish a displacement value which, in combination with the base address, will locate the decoded fixed-length word or character group in the last memory unit. In those instances where the length of the variable-length codes would become excessively long (for the less frequently occurring character groups) the original fixed-length codes are employed, each being preceded by a common "COPY" code. A special decoding procedure is invoked by this copy code.

    17.
    发明专利
    未知

    公开(公告)号：IT1150956B

    公开(公告)日：1986-12-17

    申请号：IT2260580

    申请日：1980-06-06

    Applicant: IBM

    Inventor： COCKE JOHN ,  MALM RICHARD LAVERNE ,  SHEDLETSKY JOHN JAMES

    IPC: G06F11/25 ,  G01R31/28 ,  G06F15/00 ,  G06F17/50 ,  G06F

    Abstract: A computer system for simulation of logic operations comprised of an array of specially designed parallel processors (1-31), there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory (202). Logic values simulated by one processor are communicated to other processors by a switching mechanism (33) controlled by a controller (32). If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks (35, 36) for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks (38, 39) are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.

    VIRTUAL MEMORY ADDRESS TRANSLATION MECHANISM WITH CONTROLLED DATA PERSISTENCE
    18.
    发明专利
    VIRTUAL MEMORY ADDRESS TRANSLATION MECHANISM WITH CONTROLLED DATA PERSISTENCE 未知

    公开(公告)号：CA1200917A

    公开(公告)日：1986-02-18

    申请号：CA443872

    申请日：1983-12-21

    Applicant: IBM

    Inventor： CHANG ALBERT ,  COCKE JOHN ,  MERGEN MARK F ,  RADIN GEORGE

    IPC: G06F13/00 ,  G06F11/07 ,  G06F12/00 ,  G06F12/10 ,  G06F12/14 ,  G06F9/36

    Abstract: VIRTUAL MEMORY ADDRESS TRANSLATION MECHANISM WITH CONTROLLED DATA PERSISTENCE Memory address translation and control system converts virtual memory addresses of a CPU into real memory addresses and for controlling memory functions. Address translation function comprises converting the virtual address into an effective address using a register set addressable by a small field of the CPU generated virtual address which converts the virtual address into an expanded form; and converting the effective address into a real memory address. The effective address is then used in the address translation step. To enhance the translation of frequently used virtual addresses, Translation Look-Aside Buffers (TLB) contain current effective to real address translations. The TLBs are addressed using a subset of the effective address. The contents of the addressed TLB is examined for a match with the effective address. When matched, successful address translation is possible and the real address stored in the TLB is available for system use. If not matched, the page frame tables stored in main memory are accessed for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.

    19.
    发明专利
    未知

    公开(公告)号：IT8022605D0

    公开(公告)日：1980-06-06

    申请号：IT2260580

    申请日：1980-06-06

    Applicant: IBM

    Inventor： COCKE JOHN ,  MALM RICHARD LAVERNE ,  SHEDLETSKY JOHN JAMES

    IPC: G06F11/25 ,  G01R31/28 ,  G06F15/00 ,  G06F17/50 ,  G06F

    Abstract: A computer system for simulation of logic operations comprised of an array of specially designed parallel processors (1-31), there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory (202). Logic values simulated by one processor are communicated to other processors by a switching mechanism (33) controlled by a controller (32). If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks (35, 36) for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks (38, 39) are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.

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