公开(公告)号：WO2007082227A3

公开(公告)日：2008-09-25

申请号：PCT/US2007060317

申请日：2007-01-10

Applicant: IBM ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory (100) having multiple ports per memory cell for accessing a data bit with each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plural of capacitors (102) connected together as a unitary source of capacitance (S). A first access transistor (104) is coupled between a firs one of the plurality of capacitors and a first bitline (RBL) and a second access transistor (106) is coupled between a second one of th plurality of capacitors and a second bitline (WBL) In each memory cell, a gate of the first access transistor (104) is connected to a fi wordline (RWL) and a gate of the second access transistor (106) is connected to a second wordline (WWL)

Abstract translation: 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器（100），用于利用多个存储器单元中的每一个访问数据位。 这样的存储器包括存储单元阵列，其中每个存储单元包括连接在一起的多个电容器（102）作为电容（S）的整体源。 第一存取晶体管（104）耦合在所述多个电容器中的第一个电容器中，并且第一位线（RBL）和第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线（WBL ）在每个存储单元中，第一存取晶体管（104）的栅极连接到fi字线（RWL），第二存取晶体管（106）的栅极连接到第二字线（WWL）

公开(公告)号：WO0237542A2

公开(公告)日：2002-05-10

申请号：PCT/US0146921

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  KUDELKA STEPHAN

IPC: H01L21/8242 ,  H01L21/00

CPC classification number: H01L27/10867 ,  H01L27/10876

Abstract: A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.

Abstract translation: 形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

公开(公告)号：WO0245130A3

公开(公告)日：2004-01-08

申请号：PCT/US0144625

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L27/10 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/10864 ,  H01L27/10885 ,  H01L27/10891

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports, comprising: Forming a french capacitor in a silicon substrate having a gate oxide layer, a polysilicon layer, and a top dialectric nitride layer deposited thereon; Applying a patterned mask over the array and support areas and forming recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Forming a silicide and oxide cap in the recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Applying a block mask to protect the supports while stripping the nitride layer from the array and etching the exposed polysilicon layer to the top of the gate oxide layer; Striping the nitride layer from the support region and depositing a polysilicon layer over the array and support areas; Applying a mask to pattern and form a bitline diffusion stud landing pad in the array and gate conductors for the support transistors; Saliciding the tops of the landing pad and the gate conductors; Applying an interlevel oxide layer and then opening vias in the interlevel oxide layer for establishing conductive wiring channels.

Abstract translation: 一种用于生产非常高密度的嵌入式DRAM /非常高性能的逻辑结构的方法，包括在支撑体中制造具有水银源/漏极和栅极导体双功函数MOSFET的垂直MOSFET DRAM单元，包括：在硅衬底中形成法兰电容器， 栅极氧化物层，多晶硅层和沉积在其上的顶部侧面氮化物层; 在阵列和支撑区域上施加图案化掩模并在氮化物层，多晶硅层和浅沟槽隔离区域中形成凹陷; 在氮化物层，多晶硅层和浅沟槽隔离区域的凹槽中形成硅化物和氧化物盖; 施加阻挡掩模以保护支撑物，同时从阵列剥离氮化物层并将暴露的多晶硅层蚀刻到栅极氧化物层的顶部; 从支撑区域剥离氮化物层并在阵列和支撑区域上沉积多晶硅层; 应用掩模来图案化并在阵列中形成位线扩散螺柱着陆焊盘，并在支撑晶体管上形成栅极导体; 打击着陆板和门导体的顶部; 施加层间氧化层，然后在层间氧化层中开通通孔，以建立导电布线通道。

公开(公告)号：WO0201567A3

公开(公告)日：2002-02-25

申请号：PCT/US0120221

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10841

公开(公告)号：WO0245134A3

公开(公告)日：2003-04-03

申请号：PCT/US0151214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HORN PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/60 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

Abstract translation: 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：WO0117010A9

公开(公告)日：2002-09-19

申请号：PCT/US0023850

申请日：2000-08-30

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： AKATSU HIROYUKI ,  DIVAKARUNI RAMACHANDRA ,  LEE GILL YOUNG

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L29/6659 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10873 ,  H01L27/10894

Abstract: There is disclosed the process of forming a gate conductor for a semiconductor device. The process begins with the step of providing a semiconductor substrate having a gate stack formed thereon, the gate stack including a sidewall. Dielectric spacers are formed on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer (36) and an outer spacer (38), the outer spacer being of a doped glass material. Ions are implanted into the semiconductor substrate outwardly of the dielectric spacers. The outer spacers are then removed.

Abstract translation: 公开了形成用于半导体器件的栅极导体的工艺。 该方法开始于提供其上形成有栅极堆叠的半导体衬底的步骤，栅叠层包括侧壁。 电介质间隔物形成在栅极导体侧壁上，电介质隔离物包括内部间隔物（36）和外部间隔物（38），外部间隔物是掺杂的玻璃材料。 离子在介质间隔物的外侧注入到半导体衬底中。 然后拆下外隔离物。

公开(公告)号：WO0201607A3

公开(公告)日：2002-05-23

申请号：PCT/US0120206

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  BERGNER WOLFGANG ,  BRONNER GARY B ,  GRUENING ULRIKE ,  KUDELKA STEPHEN ,  MICHAELIS ALEXANDER ,  NESBIT LARRY ,  RADENS CARL J ,  SCHLOESSER TILL ,  TEWS HEOMUT HORST

IPC: H01L21/8242

CPC classification number: H01L27/10864

Abstract: A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Abstract translation: 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。 绝缘材料沉积在存储电容器的节点导体（3）的上方。 一层硅（9）沉积在阻挡材料上。 将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：WO2012106056A3

公开(公告)日：2012-10-18

申请号：PCT/US2012020020

申请日：2012-01-03

Applicant: IBM ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  LI YING

Inventor： RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  LI YING

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L29/401 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor structure is provided that includes a semiconductor substrate 12 having a plurality of gate stacks 14' located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer 42, a work function metal layer 44 and a conductive metal 46. A spacer 22 is located on sidewalls of each gate stack and a self- aligned dielectric liner 30 is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner 30 is present on an upper surface of a semiconductor metal alloy 28. A contact metal 34 is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner 30. The structure also includes another contact metal 60 having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.

Abstract translation: 提供半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层14'的半导体衬底12。 每个栅极堆叠从底部到顶部包括高k栅极电介质层42，功函数金属层44和导电金属46.间隔物22位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫30是 存在于每个间隔件的上表面上。 每个自对准电介质衬垫30的底表面存在于半导体金属合金28的上表面上。接触金属34位于相邻的栅极叠层之间并且通过自对准电介质衬垫30与每个栅极叠层分开。 该结构还包括另一接触金属60，其具有位于接触金属的上表面上并与其直接接触的部分以及位于栅叠层中的一个的导电金属上并与其直接接触的另一部分。 还公开了使用替代栅极和非替代栅极方案形成半导体结构的方法。

公开(公告)号：WO2007115002A3

公开(公告)日：2008-11-06

申请号：PCT/US2007064380

申请日：2007-03-20

Applicant: IBM ,  DIVAKARUNI RAMACHANDRA ,  CHENG KANGGUO

Inventor： DIVAKARUNI RAMACHANDRA ,  CHENG KANGGUO

IPC: H01L21/44 ,  C01B32/50 ,  H01L21/00

CPC classification number: H01L29/7827 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10876 ,  H01L29/66666 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of forming a body contact (215) for an semiconductor-on-insulator trench device. The method including: forming set of mandrels (190) on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers (195) on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening (197) in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench (200) in the substrate in the opening; and filling the contact trench with an electrically conductive material (210) to form the contact.

Abstract translation: 一种形成用于绝缘体上半导体沟槽器件的体接触（215）的结构和方法。 该方法包括：在基板的顶表面上形成一组心轴（190），该心轴组的每个心轴布置在多边形的不同角上并在衬底的顶表面上方延伸， 一组心轴等于多边形的多个角; 在所述一组心轴的每个心轴的侧壁上形成侧壁间隔件（195），每个相邻的一对心轴的侧壁间隔件彼此合并并形成在多边形的内部区域中限定开口（197）的不间断的壁，区域 的基板暴露在开口中; 蚀刻开口中的衬底中的接触沟槽（200）; 以及用导电材料（210）填充所述接触沟槽以形成所述接触。

公开(公告)号：DE10361272B4

公开(公告)日：2012-01-05

申请号：DE10361272

申请日：2003-12-24

Applicant: QIMONDA AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  VAN ROIJEN RAYMOND

IPC: H01L21/8242 ,  H01L27/108

Abstract: Verfahren zum Ausbilden einer DRAM-Speicherzelle (100), umfassend: Ausbilden eines Grabens mit einer Grabenwandung in einem Halbleitersubstrat (10); Ausbilden eines Grabenkondensators (20) in einem unteren Bereich des Grabens mit einer dielektrischen Kondensatorschicht auf einer Innenfläche des Grabens, mit einem isolierenden Grabenkragen (110) in einem oberen Bereich des Grabenkondensators (20) und einer mittleren Kondensatorelektrode (105); Zurücksetzen der mittleren Kondensatorelektrode (105) auf eine Kondensatortiefe, wobei eine Elektrodenoberfläche verbleibt; Zurücksetzen des isolierenden Grabenkragens (110) auf eine Ebene unterhalb der Elektrodenoberfläche, wobei eine Buried-Strap-Öffnung (113) zwischen der mittleren Kondensatorelektrode (105) und der Grabenwandung ausgebildet und die Buried-Strap-Öffnung (113) mit einer ersten provisorischen Isolierschicht (112) aufgefüllt wird; Ausbilden einer Anzahl von Isolationsgräben in dem Halbleitersubstrat (10) mit einer bestimmten Isolationsgrabentiefe und Auffüllen der Isolationsgräben mit einem isolierenden Material (15); Ausbilden eines leitenden Buried-Strap (114), der mit der mittleren Kondensatorelektrode (105) in Kontakt steht und an die Grabenwandung angrenzt, wobei die...