公开(公告)号：JP2000277708A

公开(公告)日：2000-10-06

申请号：JP2000073717

申请日：2000-03-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK A ,  NESBIT LARRY ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To prevent resistance of an embedded strap of a DRAM cell from changing by the overlapping manner of a deep trench and an active region. SOLUTION: This semiconductor device contains a semiconductor substrate. At least a pair of deep trenches are formed in the substrate. A collar is formed in at least a part of the sidewall of each of the deep trenches. The inside of each of the deep trenches is filled with a trench filler 44. An embedded strap 46 is formed over the whole of each of the deep trenches and covers the upper surfaces of the trench filler 44 and the collar. An insulating region is formed between a a pair of the deep trenches. A trench upper part dielectric region 52 formed in the deep trench, so as to overlap with the embedded strap 46 of each of the deep trenches.

公开(公告)号：WO0201607A3

公开(公告)日：2002-05-23

申请号：PCT/US0120206

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  BERGNER WOLFGANG ,  BRONNER GARY B ,  GRUENING ULRIKE ,  KUDELKA STEPHEN ,  MICHAELIS ALEXANDER ,  NESBIT LARRY ,  RADENS CARL J ,  SCHLOESSER TILL ,  TEWS HEOMUT HORST

IPC: H01L21/8242

CPC classification number: H01L27/10864

Abstract: A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Abstract translation: 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。 绝缘材料沉积在存储电容器的节点导体（3）的上方。 一层硅（9）沉积在阻挡材料上。 将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：WO0195391A8

公开(公告)日：2002-03-28

申请号：PCT/US0117927

申请日：2001-06-01

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NESBIT LARRY ,  MCSTAY IRENE LENNOX ,  RADENS CARL ,  TEWS HELMUT HORST ,  DIVAKARUNI RAMA ,  MANDELMAN JACK

IPC: H01L21/8242

CPC classification number: H01L27/10861 ,  H01L27/10867

Abstract: A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner (81) is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer (79). A layer of amorphous silicon (83) is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist (83) is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar (89) along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

Abstract translation: 一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。 首先在硅衬底中形成DRAM沟槽。 然后，氮化物衬垫（81）沉积在硅沟槽壁上。 氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层（79）上。 然后在氮化物衬垫上沉积一层非晶硅（83）。 在非晶硅的氧化表面上沉积氮化硅层。 在沟槽的下部形成抗蚀剂（83），去除非晶硅顶部的露出的氮化硅层，使非晶硅层的上部露出。 然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环（89）。 非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。 氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。 在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

公开(公告)号：WO0227784A3

公开(公告)日：2003-04-10

申请号：PCT/US0142293

申请日：2001-09-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMA ,  RADENS CARL ,  NESBIT LARRY ,  BERGNER WOLFGANG

IPC: H01L21/8242 ,  H01L23/525

CPC classification number: H01L27/10861 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug (108) formed within an upper portion of the trench opening (110) and includes conductive leads (252, 254) contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology, the plug forming the gate of the vertical transistor.

Abstract translation: 垂直DRAMS中的半导体熔丝和反熔丝的结构和工艺在半导体衬底内形成的沟槽开口中提供熔丝和反熔丝。 垂直晶体管可以形成在形成在半导体衬底内的其它沟槽开口中。 熔丝形成包括形成在沟槽开口（110）的上部内的半导体插塞（108），并且包括接触半导体插头的导电引线（252,254）。 反熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括形成在半导体插头上的导电引线，至少一个导电引线，其通过反熔丝绝缘体与半导体插塞隔离。 熔丝和反熔丝中的每一个都使用一系列工艺操作来制造，这些工艺操作也用于根据垂直DRAM技术同时制造垂直晶体管，该插头形成垂直晶体管的栅极。

公开(公告)号：DE10226568A1

公开(公告)日：2003-02-06

申请号：DE10226568

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MALIK RAJEEB ,  NESBIT LARRY ,  BEINTNER JOCHEN ,  DIVAKARUNI RAMA

IPC: H01L21/762 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：DE10226569A1

公开(公告)日：2003-01-16

申请号：DE10226569

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  DEV PRAKASH ,  MALIK RAJEEV ,  NESBIT LARRY

IPC: H01L21/8242 ,  H01L27/108

Abstract: The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.

公开(公告)号：WO03005447A8

公开(公告)日：2004-02-19

申请号：PCT/GB0202961

申请日：2002-06-27

Applicant: IBM ,  IBM UK ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMACHANDRA ,  GRUENING ULRIKE ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract translation: 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。 该工艺消除了对M0金属化层的需要。

公开(公告)号：WO03005447A2

公开(公告)日：2003-01-16

申请号：PCT/GB0202961

申请日：2002-06-27

Applicant: IBM ,  IBM UK ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMACHANDRA ,  GRUENING ULRIKE ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract translation: 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域，连接焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠中制造具有硅化多晶硅层的垂直MOSFET DRAM单元。 该工艺消除了对M0金属化层的需求。

公开(公告)号：AT389242T

公开(公告)日：2008-03-15

申请号：AT05701511

申请日：2005-01-13

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  MITCHELL PETER ,  NESBIT LARRY

IPC: H01L51/30 ,  H01L21/78 ,  H01L27/28

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

公开(公告)号：AT504946T

公开(公告)日：2011-04-15

申请号：AT05707994

申请日：2005-02-10

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  KOBURGER CHARLES ,  MITCHELL PETER ,  NESBIT LARRY

IPC: H01L51/05 ,  G11C13/02 ,  H01L21/335 ,  H01L21/336 ,  H01L27/28 ,  H01L29/06 ,  H01L29/12 ,  H01L29/772 ,  H01L51/30 ,  H01L51/40

Abstract: Carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, device structures, and arrays of device structures. A stacked device structure includes a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The gate electrode has a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.