公开(公告)号：WO0201607A3

公开(公告)日：2002-05-23

申请号：PCT/US0120206

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  BERGNER WOLFGANG ,  BRONNER GARY B ,  GRUENING ULRIKE ,  KUDELKA STEPHEN ,  MICHAELIS ALEXANDER ,  NESBIT LARRY ,  RADENS CARL J ,  SCHLOESSER TILL ,  TEWS HEOMUT HORST

IPC: H01L21/8242

CPC classification number: H01L27/10864

Abstract: A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Abstract translation: 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。 绝缘材料沉积在存储电容器的节点导体（3）的上方。 一层硅（9）沉积在阻挡材料上。 将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：WO0199158A2

公开(公告)日：2001-12-27

申请号：PCT/US0119578

申请日：2001-06-19

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： BEINTNER JOCHEN ,  MICHAELIS ALEXANDER ,  GRUENING ULRIKE ,  SPINDLER OSWALD ,  GABRIC ZVONIMIR

IPC: H01L21/316 ,  H01L21/32 ,  H01L21/8242 ,  H01L21/00

CPC classification number: H01L27/10861 ,  H01L21/31612 ,  H01L21/32 ,  H01L27/1087

Abstract: A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench (104) in a silicon substrate (102), and depositing and recessing a nitride liner (112) in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide (116) is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar (116) in the trench.

Abstract translation: 根据本发明的在沟槽中形成氧化物环的方法包括在硅衬底（102）中形成沟槽（104），以及沉积和凹入沟槽中的氮化物衬垫（112）以暴露部分 的硅衬底在沟槽的侧壁上。 对硅衬底的部分上的氮化物衬垫选择性地沉积氧化物（116）。 从氮化物衬垫的表面去除残余氧化物，以在沟槽中形成套环（116）。

公开(公告)号：WO0189284A3

公开(公告)日：2002-05-30

申请号：PCT/US0115896

申请日：2001-05-16

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  MICHAELIS ALEXANDER ,  KUDELKA STEPHEN ,  SCHROEDER UWE ,  GRUENING ULRIKE

IPC: H01L21/8242

CPC classification number: H01L27/10861

Abstract: A method of using at least two insulative layers to form the isolation collar of a trench capacitor, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.

Abstract translation: 使用至少两个绝缘层形成沟槽电容器的隔离环的方法，以及由其形成的器件。 第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。 优选地，TEOS工艺和LOCOS工艺都用于形成第一层。 第二层优选是形成在氧化物层上的氮化硅层（114）。 多层用作沟槽的隔离环叠层。 第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

公开(公告)号：WO0199185A3

公开(公告)日：2002-03-28

申请号：PCT/US0119576

申请日：2001-06-19

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  LEE BRIAN S ,  MICHAELIS ALEXANDER ,  KUDLEKA STEPHAN ,  SCHROEDER UWE

IPC: H01L21/8242

CPC classification number: H01L27/10864 ,  H01L27/10876

Abstract: A method of forming a vertically-oriented device such as a DRAM storage all with a trench capacitor under a vertical transistor, using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a poertion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

Abstract translation: 使用选择性湿法蚀刻仅在沟槽中除去一部分侧壁，以及由其形成的器件，在垂直晶体管下，用沟槽电容器形成诸如DRAM存储器的垂直取向器件的方法。 虽然沟槽周边（例如，隔离环304）的作用被掩模（例如，多晶硅318）保护，但是暴露部分被选择性地湿蚀刻以从沟槽的暴露部分移除所选择的晶面，留下平坦的基板 侧壁（324）与单晶面。 单侧垂直沟槽晶体管可以形成在平坦侧壁上。 形成在单晶平面上的晶体管的垂直栅极氧化物（例如二氧化硅330）在晶体管沟道上基本上是均匀的，从而降低了泄漏的机会和从器件到器件的一致的阈值电压。 此外，沟槽加宽大大降低，从而在单面掩埋带接合器件布局中将器件增加到器件隔离距离。

公开(公告)号：WO0199162A3

公开(公告)日：2002-07-18

申请号：PCT/US0119882

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MICHAELIS ALEXANDER ,  TEWS HELMUT HORST ,  KUDELKA STEPHAN ,  GRUENING ULRIKE ,  BEINTNER JOCHEN ,  SCHROEDER UWE

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/04 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28211 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/42368 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of using a selective etch to provide a desired crystal plane orientation on the sidewalls of a deep trench located in a semiconductor substrate, and the device formed therefrom. Preferably, a crystal plane sidewall (212) is used for the channel region, and crystal planes (216) are used in the corner regions of the trench. Gate oxidation may then be performed such that the oxide is thicker in the corner regions (222) than on the oxide (218, 220) on the primary sides of the trench, resulting in self isolation of the corner areas from the transistor channel/active area (224). In addition, the structure is relatively insensitive to active area/deep trench misalignment.

Abstract translation: 一种使用选择性蚀刻以在位于半导体衬底中的深沟槽的侧壁上提供期望的晶面取向的方法和由其形成的器件。 优选地，在沟道区域中使用<100>晶面侧壁（212），并且在沟槽的拐角区域中使用<110>晶面（216）。 然后可以执行栅极氧化，使得在角区域（222）中的氧化物比在沟槽的初级侧上的氧化物（218,220）上更厚，导致拐角区域与晶体管沟道/活性物质的自我隔离 区域（224）。 此外，该结构对有源区/深沟槽未对准相对不敏感。

公开(公告)号：WO0191180A3

公开(公告)日：2002-07-18

申请号：PCT/US0115757

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TEWS HELMUT HORST ,  LEE BRIAN S ,  MICHAELIS ALEXANDER ,  SCHROEDER UWE ,  KUDELKA STEPHEN

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L27/10864 ,  H01L21/76237 ,  H01L21/823487 ,  H01L27/10841 ,  H01L27/10867

Abstract: A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

Abstract translation: 使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。 电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。 低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。 然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。 然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分 沟槽暴露进一步加工。 或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。 自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

公开(公告)号：DE60036869D1

公开(公告)日：2007-12-06

申请号：DE60036869

申请日：2000-07-07

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： KUDELKA STEPHAN ,  MICHAELIS ALEXANDER

IPC: H01L21/306 ,  H01L21/8242 ,  H01L27/108

Abstract: In accordance with the present invention, a method for etching back filler material for a buried strap for deep trench capacitors includes the steps of forming a trench in a substrate, filling the trench with a first filler material, recessing the first filler material to a predetermined depth relative to a dielectric collar formed in the trench, forming a divot by etching back the dielectric collar, depositing a liner over the first filler material and portions of the substrate exposed by the formation of the trench, and depositing a second filler material on the liner. A surface of the second filler material is prepared by etching the surface with a wet etchant to provide a hydrogen terminated silicon surface. Wet etching the second filler material is performed to etch back the second filler material selective to the liner and the substrate. The second filler material is etched to form a buried strap.