公开(公告)号：DE4026912A1

公开(公告)日：1991-02-28

申请号：DE4026912

申请日：1990-08-25

Applicant: IBM

Inventor： BEALKOWSKI RICHARD ,  BLACKLEDGE JUN JOHN WILEY ,  CRONK DOYLE STANFILL ,  DAYAN RICHARD ALAN ,  KINNEAR SCOTT GERARD ,  KOVACH GEORGE D ,  PALKA JUN MATTHEW STEPHEN ,  SACHSENMAIER ROBERT ,  ZYVOLOSKI KEVIN MARSHALL ,  DIXON JERRY DUANE ,  MCNEILL ANDREW BOYCE ,  WACHTEL EDWARD IRVING

IPC: G06F13/10 ,  G06F9/445 ,  G06F12/14 ,  G06F21/22

Abstract: An apparatus and method for protecting BIOS stored on a direct access storage device (62) into a personal computer system (10). The personal computer system (JO) comprises a system processor (26), a system planar (24), a random access main memory (32), a read only memory (36), a protection means and at least one direct access storage device (62). The read only memory (36) includes a first portion of BIOS and data representing the type of system processor (26) and system planar (24) I/O configuration. The first portion of BIOS initializes the system (10) and the direct access storage device (62), and resets the protection means in order to read in a master boot record into the random access memory (32) from a protectable partition on the direct access storage device (62). The master boot record includes a data segment and an executable code segment. The data segment includes data representing system hardware and a system configuration which is supported by the master boot record. The first BIOS portion confirms the master boot record is compatible with the system hardware by verifying that the data from the data segment of the master boot record agrees with the system processor (26), system planar (24), and planar (24) I/O configuration. If the master boot record is compatible with the system hardware, the first BIOS portion vectors the system processor (26) to execute the executable code segment of the master boot record. The executable code segment confirms that the system configuration has not changed and loads in the remaining BIOS portion from the same protectable partition on the direct access storage device (62) into random access memory (32). The executable code segment then verifies the authenticity of the remaining BIOS portion and vectors the system processor (26) to begin executing the BIOS now in random access memory. BIOS, executing in random access memory (32), then activates the protection means to prevent further access to the protectable partition. BIOS boots up the operating system to begin operation of the personal computer system.

公开(公告)号：BE1001066A4

公开(公告)日：1989-06-27

申请号：BE8701439

申请日：1987-12-16

Applicant: IBM

Inventor： DIXON JERRY DUANE ,  SOTOMAYOR GUY GIL JR

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/16 ,  G11B20/18 ,  G06F ,  G11B

Abstract: Dans un système d'antémémoire DASD dans lequel des pages de secteurs de données sont emmagasinées par lecture dans un secteur adjacents pour un accès ultérieur, des erreurs dans le milieu d'emmagasinage àdisque provoque la génération de signaux d'erreur. Ces erreurs sont traitées par l'emmagasinage d'indications des secteurs qui présentent des erreurs et des sedteurs qui n'en présentent pas, et par l'accès à ces indications en réponses à des demandes ultérieures pour ces secteurs. Ces indicatitons sont emmagasinées dans chaque page de antémémoire. De plus, on maintient unhistorique des pages et des secteurs qu'elle contient et qui ont été précédemment placés dans antémémoire.

公开(公告)号：DE2716905A1

公开(公告)日：1977-11-17

申请号：DE2716905

申请日：1977-04-16

Applicant: IBM

Inventor： DIXON JERRY DUANE

IPC: G11B15/087 ,  G06F3/06 ,  G11B20/12 ,  G11B20/14 ,  G11B27/10 ,  G06F7/28 ,  G11B5/02

Abstract: Signals generated by double frequency magnetic recording are received by logic which is controlled, and sensed, by a sequence of program instructions from a microprocessor. In particular, a special pattern of signals is to be recognized. The special pattern of signals is known in the magnetic disc recording art as an address mark which is a unique pattern of interspersed clock signals and data signals. The pattern is made more unique from any other pattern of data by the fact that certain of the clock signals are missing. The ability to utilize a microprocessor, which is relatively slow, in a magnetic recording system in which the bit rate is relatively fast, is enhanced by a particular processor program instruction which is effective to access a next following instruction from program storage and then stop the clock of the processor. The clock is re-started, and therefore execution of the next instruction initiated, upon receipt of a timing signal from the logic receiving the signals to be detected.

公开(公告)号：IN177289B

公开(公告)日：1996-12-21

申请号：IN586MA1990

申请日：1990-07-24

Applicant: IBM

Inventor： BEALKOWSKI RICHARD ,  BLACKLEDGE JOHN WILEY ,  CRONK DOYLE STANFILL ,  DAYAN RICHARD ALAN ,  KINNEAR SCOTT GERARD ,  PALKA MATTHEW STEPHEN ,  SACHSENMAIER ROBERT ,  ZYLVOLOSKI KEVIN MARSHALL ,  DIXON JERRY DUANE ,  MCNEILL ANDREW BOYCE ,  WACHTEL EDWARD IRVING ,  KOVACH GEORGE D

IPC: G06F15/40

公开(公告)号：DE69024111D1

公开(公告)日：1996-01-25

申请号：DE69024111

申请日：1990-06-11

Applicant: IBM

Inventor： DIXON JERRY DUANE ,  KEENER DON STEVEN ,  LOCKER HOWARD JEFFREY ,  MARAZAS GERALD ALLAN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN

IPC: G06F13/14 ,  G06F12/06

Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

公开(公告)号：AT131640T

公开(公告)日：1995-12-15

申请号：AT90306343

申请日：1990-06-11

Applicant: IBM

Inventor： DIXON JERRY DUANE ,  KEENER DON STEVEN ,  LOCKER HOWARD JEFFREY ,  MARAZAS GERALD ALLAN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN

IPC: G06F13/14 ,  G06F12/06

Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

公开(公告)号：DE3585496D1

公开(公告)日：1992-04-09

申请号：DE3585496

申请日：1985-10-15

Applicant: IBM

Inventor： DIXON JERRY DUANE ,  FARRELL ROBERT HENRI ,  MARAZAS GERALD A ,  MCNEILL JR ,  MERCKEL GERALD ULRICH

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/16 ,  G06F12/00 ,  G06F12/08 ,  G06F12/10 ,  G06F11/08

Abstract: A redundant error-detecting addressing method and system for use in a cache memory. A directory converts togical data addresses to physical addresses in the cache where the data is stored in blocks. The blocks are expanded to include redundant addressing information such as the logical data address and the physical cache address. When a block is accessed from the cache, the redundant addressing is compared to the directory addressing information to confirm that the correct data has been accessed.

公开(公告)号：DE3381542D1

公开(公告)日：1990-06-13

申请号：DE3381542

申请日：1983-05-19

Applicant: IBM

Inventor： BANDY PETER BURGHARDT ,  VERDOORN JR ,  SCHMITT STEPHEN ALOIS ,  NEELY JACK DILLWORTH ,  MERCKEL GERALD ULRICH ,  FARREL ROBERT HENRY ,  DIXON JERRY DUANE

IPC: G06F3/06 ,  G06F17/30 ,  G06F15/40

公开(公告)号：DE3380645D1

公开(公告)日：1989-11-02

申请号：DE3380645

申请日：1983-10-26

Applicant: IBM

Inventor： DIXON JERRY DUANE ,  MARAZAS GERALD ALLAN ,  MERCKEL GERALD ULRICH ,  MCNEILL ANDREW BOYCE

IPC: G06F12/08 ,  G06F12/0842 ,  G06F12/0866

公开(公告)号：FR2613506A1

公开(公告)日：1988-10-07

申请号：FR8717531

申请日：1987-12-09

Applicant: IBM

Inventor： DIXON JERRY DUANE ,  SOTOMAYOR GUY GIL JR

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/16 ,  G11B20/18 ,  G06F7/28 ,  G06F11/00

Abstract: In a DASD caching system, in which pages of sectors of data are stored by reading in a desired sector and prefetching a plurality of adjacent sectors for later access, errors in disk storage media cause error signals to be generated. Such errors are handled by storing indications of which sectors have errors and which do not, and accessing such indications in response to later requests for such sectors. Such indications are stored in each page in the cache. Further, a history is maintained of which pages and sectors therein, were placed in the cache in the past.