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    1.
    发明专利
    未知

    公开(公告)号：DE69024111T2

    公开(公告)日：1996-06-20

    申请号：DE69024111

    申请日：1990-06-11

    Applicant: IBM

    Inventor： DIXON JERRY DUANE ,  KEENER DON STEVEN ,  LOCKER HOWARD JEFFREY ,  MARAZAS GERALD ALLAN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN

    IPC: G06F13/14 ,  G06F12/06

    Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

    2.
    发明专利
    未知

    公开(公告)号：DE69023701D1

    公开(公告)日：1996-01-04

    申请号：DE69023701

    申请日：1990-05-31

    Applicant: IBM

    Inventor： MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN ,  REID EDDIE MILLER

    IPC: G06F3/00 ,  G06F13/40 ,  G06F15/00 ,  H01R9/00 ,  H01R29/00

    Abstract: A plug-in feature board (10) for a computer system has special circuitry to permit the board to customise itself to the particular slot into which it is inserted. Computers of the type intended for individual use or use in small networks typically provide insertion slots including connectors to permit feature boards to be added and connected to a bus of the computer for adding new function or capacity. As the computing power of such systems has increased there have been increases in the size of portions of the connecting bus to permit improvements in data transfer performance. In a given computer system there are often two or more bus connector (32) configurations presented in respective slots. By so converting electrical states at selected connector positions as to provide signal information for determining bus configuration for the slot, special logic provided on the board is enabled to determine the characteristics of the slot in which the board is placed and customises the board to respond or limit response in accordance with the requirements for that configuration. By so adapting to the slot the board achieves enhanced applicability and avoids certain system disabling malfunctions which can occur when a board is plugged into a slot for which it is not configured.

    FUNCTIONAL BOARD FOR COMPUTER SYSTEM
    3.
    发明专利
    FUNCTIONAL BOARD FOR COMPUTER SYSTEM 未知

    公开(公告)号：CZ284019B6

    公开(公告)日：1998-07-15

    申请号：CS291790

    申请日：1990-06-12

    Applicant: IBM

    Inventor： MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN ,  REID EDDIE MILLER

    IPC: G06F3/00 ,  G06F13/40 ,  G06F15/00 ,  H01R9/00 ,  H01R29/00

    Abstract: A plug-in feature board (10) for a computer system has special circuitry to permit the board to customise itself to the particular slot into which it is inserted. Computers of the type intended for individual use or use in small networks typically provide insertion slots including connectors to permit feature boards to be added and connected to a bus of the computer for adding new function or capacity. As the computing power of such systems has increased there have been increases in the size of portions of the connecting bus to permit improvements in data transfer performance. In a given computer system there are often two or more bus connector (32) configurations presented in respective slots. By so converting electrical states at selected connector positions as to provide signal information for determining bus configuration for the slot, special logic provided on the board is enabled to determine the characteristics of the slot in which the board is placed and customises the board to respond or limit response in accordance with the requirements for that configuration. By so adapting to the slot the board achieves enhanced applicability and avoids certain system disabling malfunctions which can occur when a board is plugged into a slot for which it is not configured.

    PHYSICAL PARTITIONING OF LOGICALLY CONTINUOUS BUS
    4.
    发明专利
    PHYSICAL PARTITIONING OF LOGICALLY CONTINUOUS BUS 未知

    公开(公告)号：CA2092631C

    公开(公告)日：1997-04-08

    申请号：CA2092631

    申请日：1993-03-12

    Applicant: IBM

    Inventor： KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  SCHEIERN KEVIN LEE ,  NEWSOM THOMAS HAROLD ,  VOORHEES RICHARD W ,  WACHTEL EDWARD IRVING

    IPC: G06F13/36 ,  G06F13/40 ,  G06F13/16

    Abstract: Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

    FUNCTIONAL BOARD OF A COMPUTER
    7.
    发明专利
    FUNCTIONAL BOARD OF A COMPUTER 未知

    公开(公告)号：PL285595A1

    公开(公告)日：1991-04-08

    申请号：PL28559590

    申请日：1990-06-12

    Applicant: IBM

    Inventor： MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN ,  REID EDDIE MILLER

    IPC: G06F13/40 ,  G06F3/00 ,  G06F15/00 ,  H01R9/00 ,  H01R29/00 ,  G06F13/00

    Abstract: A plug-in feature board (10) for a computer system has special circuitry to permit the board to customise itself to the particular slot into which it is inserted. Computers of the type intended for individual use or use in small networks typically provide insertion slots including connectors to permit feature boards to be added and connected to a bus of the computer for adding new function or capacity. As the computing power of such systems has increased there have been increases in the size of portions of the connecting bus to permit improvements in data transfer performance. In a given computer system there are often two or more bus connector (32) configurations presented in respective slots. By so converting electrical states at selected connector positions as to provide signal information for determining bus configuration for the slot, special logic provided on the board is enabled to determine the characteristics of the slot in which the board is placed and customises the board to respond or limit response in accordance with the requirements for that configuration. By so adapting to the slot the board achieves enhanced applicability and avoids certain system disabling malfunctions which can occur when a board is plugged into a slot for which it is not configured.

    Physical partioning of logically continuous bus
    9.
    发明专利
    Physical partioning of logically continuous bus 未知

    公开(公告)号：SG42891A1

    公开(公告)日：1997-10-17

    申请号：SG1996000456

    申请日：1993-05-04

    Applicant: IBM

    Inventor： KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  SCHEIERN KEVIN LEE ,  VOORHEES RICHARD W ,  WACHTEL EDWARD IRVING

    IPC: G06F13/40 ,  G06F13/36

    Abstract: Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

    10.
    发明专利
    未知

    公开(公告)号：DE69024111D1

    公开(公告)日：1996-01-25

    申请号：DE69024111

    申请日：1990-06-11

    Applicant: IBM

    Inventor： DIXON JERRY DUANE ,  KEENER DON STEVEN ,  LOCKER HOWARD JEFFREY ,  MARAZAS GERALD ALLAN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN

    IPC: G06F13/14 ,  G06F12/06

    Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

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