公开(公告)号：WO2005027192A3

公开(公告)日：2006-12-21

申请号：PCT/US2004028163

申请日：2004-08-30

Applicant: IBM ,  DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

Inventor： DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

Abstract translation: 提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力 在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。 应力由第一半导体晶格失配的第二半导体层施加。 第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。

公开(公告)号：WO2005029545A3

公开(公告)日：2005-11-03

申请号：PCT/US2004030289

申请日：2004-09-14

Applicant: IBM ,  DOKUMACI OMER ,  DORIS BRUCE ,  GUARINI KATHRYN ,  HEGDE SURYANARAYAN ,  IEONG MEIKEI ,  JONES ERIN

Inventor： DOKUMACI OMER ,  DORIS BRUCE ,  GUARINI KATHRYN ,  HEGDE SURYANARAYAN ,  IEONG MEIKEI ,  JONES ERIN

IPC: H01L20060101 ,  H01L21/033 ,  H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

Abstract: A double-gate transistor has front (8) (upper) and back (2) gates aligned laterally by a process of forming symmetric sidewalls (10) in proximity to the front gate and then oxidizing the back gate electrode (2) at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide (13) on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode (8). Optionally, an angled implant (123) from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant (128) across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

Abstract translation: 双栅极晶体管具有通过在前栅极附近形成对称侧壁（10）并随后在一定温度下氧化背栅电极（2）的工艺横向对准的前（8）（上）和后（2） 至少1000度，时间足以缓解结构中的应力，氧化物从晶体管侧面渗透以增厚外边缘上的背栅氧化层（13），在中心处留下有效厚度的栅氧化层 ，与前栅电极（8）对齐。 可选地，来自氧化物增强物质的侧面的成角度的注入物（123）鼓励外部注入区域中的相对较厚的氧化物，并且越过晶体管主体的氧化物阻滞注入物（128）延迟了在垂直方向上的氧化，由此允许 氧化的横向范围。

公开(公告)号：AT551727T

公开(公告)日：2012-04-15

申请号：AT04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER ,  DORIS BRUCE ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

Abstract: A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.

公开(公告)号：AU2002239671A1

公开(公告)日：2002-11-11

申请号：AU2002239671

申请日：2001-12-27

Applicant: IBM

Inventor： KAPLAN RICHARD ,  DOKUMACI OMER ,  KHARE MUKESH ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, and Xe; and mixtures thereof.