公开(公告)号：EP1382064A4

公开(公告)日：2008-05-07

申请号：EP01987463

申请日：2001-12-27

Applicant: IBM

Inventor： DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G ,  KAPLAN RICHARD ,  KHARE MUKESH

IPC: H01L21/3205 ,  H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/31 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, C1, He, Ar, Kr, and Xe; and mixtures thereof.

公开(公告)号：JP2002324903A

公开(公告)日：2002-11-08

申请号：JP2002068920

申请日：2002-03-13

Applicant: IBM

Inventor： KHARE MUKESH ,  AGNELLO PAUL D ,  CHOU ANTHONY I ,  HOOK TERENCE B ,  MOCUTA ANDA C

IPC: H01L21/74 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method and circuit configuration effective for reducing plasma-induced charging damage on a device fabricated on a silicon-on- insulator(SOI) substrate. SOLUTION: An SOI circuit configuration effective for minimizing plasma- induced charging damage during fabrication comprises formation of charge collectors connected to the gate electrode and a semiconductor body, wherein each of the charge collectors has the same or substantially the same shape and dimension. The formation of a connecting structure between a device formed on the SOI substrate and the substrate is delayed until the later stages of processing.

公开(公告)号：WO02089180A3

公开(公告)日：2003-02-06

申请号：PCT/US0149571

申请日：2001-12-27

Applicant: IBM

Inventor： DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G ,  KAPLAN RICHARD ,  KHARE MUKESH

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners (20) of a Si-containing transistor having a gate conductor (16) and a dielectric cap (18), and exposing the transistor including implanted transistor gate corners (20) to an oxidizing ambient. The ions employed in the implant step include Si, non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, C1, He, Ar, Kr, and Xe; and mixtures thereof.

Abstract translation: 提供了一种提高晶体管栅极角氧化速率的方法，而不显着增加整体处理方案的热预算。 具体地，本发明的方法包括将离子注入到具有栅极导体（16）和电介质盖（18）的含硅晶体管的栅极拐角（20）中，并且使包括注入的晶体管栅极角（20）的晶体管暴露， 到氧化环境。 在注入步骤中使用的离子包括Si，不延迟氧化离子如O，Ge，As，B，P，In，Sb，Ga，F，Cl，He，Ar，Kr和Xe; 及其混合物。

公开(公告)号：AU2002239671A1

公开(公告)日：2002-11-11

申请号：AU2002239671

申请日：2001-12-27

Applicant: IBM

Inventor： KAPLAN RICHARD ,  DOKUMACI OMER ,  KHARE MUKESH ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, and Xe; and mixtures thereof.