中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

30 records (took 0.018 seconds)

    DYNAMIC WAVE-PIPELINED INTERFACE APPARATUS AND METHODS THEREFOR
    11.
    发明专利
    DYNAMIC WAVE-PIPELINED INTERFACE APPARATUS AND METHODS THEREFOR 未知

    公开(公告)号：HU0105099A2

    公开(公告)日：2002-04-29

    申请号：HU0105099

    申请日：2000-03-03

    Applicant: IBM

    Inventor： DREPS DANIEL MARK ,  FERRAIOLO FRANK DAVID ,  GOWER KEVIN CHARLES

    IPC: G06F13/38 ,  G06F13/42 ,  H04L7/04

    Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

    ELASTIC INTERFACE APPARATUS AND METHOD THEREFOR
    12.
    发明专利
    ELASTIC INTERFACE APPARATUS AND METHOD THEREFOR 未知

    公开(公告)号：CA2366898A1

    公开(公告)日：2000-09-14

    申请号：CA2366898

    申请日：2000-03-03

    Applicant: IBM

    Inventor： FERRAIOLO FRANK DAVID ,  DREPS DANIEL MARK ,  GOWER KEVIN CHARLES

    IPC: G06F13/42 ,  G06F5/06 ,  H04L7/00 ,  H04L7/02

    Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage i n the corresponding storage unit. Data is sequentially output from each storag e unit in synchrony with the local clock on a target cycle of the local clock.

    ELASTIC INTERFACE APPARATUS AND METHOD THEREFOR
    15.
    发明专利
    ELASTIC INTERFACE APPARATUS AND METHOD THEREFOR 未知

    公开(公告)号：PL350133A1

    公开(公告)日：2002-11-04

    申请号：PL35013300

    申请日：2000-03-03

    Applicant: IBM

    Inventor： DREPS DANIEL MARK ,  FERRAIOLO FRANK DAVID ,  GOWER KEVIN CHARLES

    IPC: G06F13/42 ,  G06F5/06 ,  H04L7/00 ,  H04L7/02

    Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

    16.
    发明专利
    未知

    公开(公告)号：BR0009251A

    公开(公告)日：2001-11-20

    申请号：BR0009251

    申请日：2000-03-03

    Applicant: IBM

    Inventor： DREPS DANIEL MARK ,  FERRAIOLO FRANK DAVID ,  GOWER KEVIN CHARLES

    IPC: G06F13/38 ,  G06F13/42 ,  H04L7/04

    Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

    DYNAMIC WAVE-PIPELINED INTERFACE APPARATUS AND METHODS THEREFOR
    17.
    发明专利
    DYNAMIC WAVE-PIPELINED INTERFACE APPARATUS AND METHODS THEREFOR 未知

    公开(公告)号：CA2365288A1

    公开(公告)日：2000-09-14

    申请号：CA2365288

    申请日：2000-03-03

    Applicant: IBM

    Inventor： FERRAIOLO FRANK DAVID ,  GOWER KEVIN CHARLES ,  DREPS DANIEL MARK

    IPC: G06F13/38 ,  G06F13/42 ,  H04L7/04

    Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is se t according to an initialisation procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centred in a data valid window.

    Strobe offset in bidirectional memory strobe configurations
    18.
    发明专利
    Strobe offset in bidirectional memory strobe configurations 未知

    公开(公告)号：GB2490432A

    公开(公告)日：2012-10-31

    申请号：GB201210237

    申请日：2011-01-19

    Applicant: IBM

    Inventor： KIM KYU-HYOUN ,  DREPS DANIEL MARK ,  SORNA MICHAEL ,  KERR MICHAEL KEVIN ,  MANN DAVID WILLIAM ,  MOSSMAN JAMES ,  GOWER KEVIN ,  TREMAINE ROBERT ,  ZEVIN WILLIAM MARK

    IPC: G06F13/16 ,  G06F13/42 ,  G11C7/10

    Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

    20.
    发明专利
    未知

    公开(公告)号：ES2195873T3

    公开(公告)日：2003-12-16

    申请号：ES00907775

    申请日：2000-03-03

    Applicant: IBM

    Inventor： DREPS DANIEL MARK ,  FERRAIOLO FRANK DAVID ,  GOWER KEVIN CHARLES

    IPC: G06F13/38 ,  G06F13/42 ,  H04L7/04

    Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

Patent Agency Ranking