CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK
    1.
    发明申请
    CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK 审中-公开
    循环冗余码用于高速串行链路

    公开(公告)号:WO2010000623A3

    公开(公告)日:2010-02-25

    申请号:PCT/EP2009057580

    申请日:2009-06-18

    CPC classification number: H04L1/0056 G06F11/10

    Abstract: A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.

    Abstract translation: 一种用于提供用于高速串行链路的循环冗余码(CRC)的系统和方法。 该系统包括级联互连存储器系统,其包括存储器控制器,存储器集线器设备和下游链路。 下游链路与存储器控制器和存储器集线器设备通信,并且包括用于将多个传输下行帧从存储器控制器发送到存储器集线器设备的至少十三个信号通道。 下游帧的一部分包括用于检测下游帧中的错误的下行CRC位。 下行CRC比特能够检测到车道故障,转移故障和高达五位随机错误中的任何一个。

    DISTRIBUTED AUTONOMOUS POWER MANAGEMENT IN A MEMORY SYSTEM

    公开(公告)号:WO2008017625A3

    公开(公告)日:2008-04-10

    申请号:PCT/EP2007057916

    申请日:2007-07-31

    Abstract: Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory controller, a plurality of memory devices, and a control unit external to the memory controller. The memory devices are in communication with the memory controller via the memory bus, with one or more of the memory devices being associated with a group. The control unit autonomously manages power within and for the group of memory devices.

    A HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS
    3.
    发明申请
    A HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS 审中-公开
    具有容错地址和命令总线的高可靠性存储器模块

    公开(公告)号:WO2004090723A3

    公开(公告)日:2005-05-12

    申请号:PCT/GB2004001593

    申请日:2004-04-13

    Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register.

    Abstract translation: 具有容错地址和命令总线的高可靠性双列直插式存储器模块,用于服务器。 存储器模块是设置有多个触点的卡,其中一些触点是冗余的,多个DRAM,锁相环,2或32K位串行EE PROM和具有纠错码的28位和1至2寄存器 (ECC),奇偶校验,用于通过独立总线读取的多字节故障报告电路和用于确定和报告耦合到服务器的存储器接口芯片和存储器控制器或处理器的可纠正错误和不可校正错误状况的实时错误行, 存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。

    CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK
    4.
    发明申请
    CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK 审中-公开
    用于高速串行链路的循环冗余码

    公开(公告)号:WO2010000623A4

    公开(公告)日:2010-04-22

    申请号:PCT/EP2009057580

    申请日:2009-06-18

    CPC classification number: H04L1/0056 G06F11/10

    Abstract: A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.

    Abstract translation: 一种用于提供用于高速串行链路的循环冗余码(CRC)的系统和方法。 该系统包括级联互连存储器系统,其包括存储器控制器,存储器集线器设备和下游链路。 下游链路与存储器控制器和存储器集线器设备通信并且包括至少十三条信道,用于从存储器控制器向存储器集线器设备传输多传送下游帧。 下游帧的一部分包括下游CRC比特以检测下游帧中的错误。 下行CRC位能够检测到通道故障,传输故障和高达5位随机错误中的任何一个。

    READ DATA FLOW CONTROL IN A CASCADE INTERCONNECT MEMORY SYSTEM
    5.
    发明申请
    READ DATA FLOW CONTROL IN A CASCADE INTERCONNECT MEMORY SYSTEM 审中-公开
    在CASCADE INTERCONNECT MEMORY系统中读取数据流控制

    公开(公告)号:WO2010000554A1

    公开(公告)日:2010-01-07

    申请号:PCT/EP2009056814

    申请日:2009-06-03

    CPC classification number: G06F13/4243 G11C5/04 Y02D10/14 Y02D10/151

    Abstract: Systems, methods and a computer program for providing read flow control in a cascade interconnect memory system. A hub device includes an interface to a channel in a cascade interconnect memory system for connecting the hub device to an upstream hub device or a memory controller. The channel includes an upstreatn-bus and a downstream bus. The hub device also includes read data flow control logic for determining when to transmit data on the upstream bus. The determining is responsive to an order of commands received on the downstream bus and to current traffic on the upstream bus. Applications include the Advanced Memory Buffer (AMB) on a Fully Buffered DIMM (FBD).

    Abstract translation: 用于在级联互连存储器系统中提供读取流控制的系统,方法和计算机程序。 集线器设备包括到级联互连存储器系统中的通道的接口,用于将集线器设备连接到上游集线器设备或存储器控制器。 该通道包括一个上行巴士和一个下游巴士。 集线器设备还包括用于确定何时在上游总线上传输数据的读数据流控制逻辑。 该确定响应于在下游总线上接收的命令的顺序以及上游总线上的当前流量。 应用程序包括完全缓冲DIMM(FBD)上的高级内存缓冲区(AMB)。

    DISTRIBUTED AUTONOMOUS POWER MANAGEMENT IN A MEMORY SYSTEM
    7.
    发明申请
    DISTRIBUTED AUTONOMOUS POWER MANAGEMENT IN A MEMORY SYSTEM 审中-公开
    存储系统中的分布式自治电源管理

    公开(公告)号:WO2008017625B1

    公开(公告)日:2008-05-29

    申请号:PCT/EP2007057916

    申请日:2007-07-31

    Abstract: Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory controller, a plurality of memory devices, and a control unit external to the memory controller. The memory devices are in communication with the memory controller via the memory bus, with one or more of the memory devices being associated with a group. The control unit autonomously manages power within and for the group of memory devices.

    Abstract translation: 在存储器系统中提供分布式自治电源管理的系统和方法。 实施例包括用于存储和检索处理系统的数据的存储器系统。 存储器系统包括用于接收和响应存储器访问请求的存储器控​​制器,与存储器控制器通信的存储器总线,多个存储器设备以及存储器控制器外部的控制单元。 存储器装置经由存储器总线与存储器控制器通信,其中一个或多个存储器装置与组相关联。 控制单元自主管理该组内存设备内的电力。

    MEMORY SYSTEMS FOR AUTOMATED COMPUTING MACHINERY
    8.
    发明申请
    MEMORY SYSTEMS FOR AUTOMATED COMPUTING MACHINERY 审中-公开
    自动计算机的存储系统

    公开(公告)号:WO2007135077B1

    公开(公告)日:2008-01-17

    申请号:PCT/EP2007054794

    申请日:2007-05-16

    CPC classification number: G06F13/1684 G06F13/1673 G06F13/1678 Y02D10/14

    Abstract: Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.

    Abstract translation: 公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。 出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。 第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。

    Abtastsignalverschiebung in Konfigurationen mit bidirektionalen Speicherabtastsignalen

    公开(公告)号:DE112011100118T5

    公开(公告)日:2012-11-08

    申请号:DE112011100118

    申请日:2011-01-19

    Applicant: IBM

    Abstract: Ein Verfahren und eine Vorrichtung zum Ermitteln der ordnungsgemäßen zeitlichen Abstimmung für das Empfangen einer von einem adressierten Speicherchip auf einem bidirektionalen Data Strobe gesendeten normalen Umschaltung in einem Hostcomputer in einem Speichersystem. Es wird eine Verschiebung in dem Data Strobe hergestellt, entweder durch Ausgabe des Befehls an den adressierten Speicherchip während eines Einarbeitungszeitraums, den Data Strobe in einen bekannten Zustand zu bringen, oder durch Bereitstellen einer Spannungsverschiebung zwischen einer wahren und einer komplementären Phase in dem Data Strobe oder durch Bereitstellen einer Schaltkreisvorspannung in einem Differenzempfänger auf dem Hostcomputer, der das Data Strobe empfängt. Eine Reihe von Lesebefehlen wird von dem Hostcomputer an den adressierten Speicherchip gesendet, der durch Senden der normalen Umschaltung reagiert. Die zeitliche Abstimmung des Empfangens der normalen Umschaltung, die von dem Hostcomputerchip empfangen wird, wird so lange angepasst, bis die normale Umschaltung ordnungsgemäß empfangen wird.

    Abtastsignalverschiebung in Konfigurationen mit bidirektionalen Speicherabtastsignalen

    公开(公告)号:DE112011100118B4

    公开(公告)日:2015-01-08

    申请号:DE112011100118

    申请日:2011-01-19

    Applicant: IBM

    Abstract: Ein Verfahren und eine Vorrichtung zum Ermitteln der ordnungsgemäßen zeitlichen Abstimmung für das Empfangen einer von einem adressierten Speicherchip auf einem bidirektionalen Data Strobe gesendeten normalen Umschaltung in einem Hostcomputer in einem Speichersystem. Es wird eine Verschiebung in dem Data Strobe hergestellt, entweder durch Ausgabe des Befehls an den adressierten Speicherchip während eines Einarbeitungszeitraums, den Data Strobe in einen bekannten Zustand zu bringen, oder durch Bereitstellen einer Spannungsverschiebung zwischen einer wahren und einer komplementären Phase in dem Data Strobe oder durch Bereitstellen einer Schaltkreisvorspannung in einem Differenzempfänger auf dem Hostcomputer, der das Data Strobe empfängt. Eine Reihe von Lesebefehlen wird von dem Hostcomputer an den adressierten Speicherchip gesendet, der durch Senden der normalen Umschaltung reagiert. Die zeitliche Abstimmung des Empfangens der normalen Umschaltung, die von dem Hostcomputerchip empfangen wird, wird so lange angepasst, bis die normale Umschaltung ordnungsgemäß empfangen wird.

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