Abstract:
A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.
Abstract:
Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory controller, a plurality of memory devices, and a control unit external to the memory controller. The memory devices are in communication with the memory controller via the memory bus, with one or more of the memory devices being associated with a group. The control unit autonomously manages power within and for the group of memory devices.
Abstract:
A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register.
Abstract:
A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.
Abstract:
Systems, methods and a computer program for providing read flow control in a cascade interconnect memory system. A hub device includes an interface to a channel in a cascade interconnect memory system for connecting the hub device to an upstream hub device or a memory controller. The channel includes an upstreatn-bus and a downstream bus. The hub device also includes read data flow control logic for determining when to transmit data on the upstream bus. The determining is responsive to an order of commands received on the downstream bus and to current traffic on the upstream bus. Applications include the Advanced Memory Buffer (AMB) on a Fully Buffered DIMM (FBD).
Abstract:
A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.
Abstract:
Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory controller, a plurality of memory devices, and a control unit external to the memory controller. The memory devices are in communication with the memory controller via the memory bus, with one or more of the memory devices being associated with a group. The control unit autonomously manages power within and for the group of memory devices.
Abstract:
Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
Abstract:
Ein Verfahren und eine Vorrichtung zum Ermitteln der ordnungsgemäßen zeitlichen Abstimmung für das Empfangen einer von einem adressierten Speicherchip auf einem bidirektionalen Data Strobe gesendeten normalen Umschaltung in einem Hostcomputer in einem Speichersystem. Es wird eine Verschiebung in dem Data Strobe hergestellt, entweder durch Ausgabe des Befehls an den adressierten Speicherchip während eines Einarbeitungszeitraums, den Data Strobe in einen bekannten Zustand zu bringen, oder durch Bereitstellen einer Spannungsverschiebung zwischen einer wahren und einer komplementären Phase in dem Data Strobe oder durch Bereitstellen einer Schaltkreisvorspannung in einem Differenzempfänger auf dem Hostcomputer, der das Data Strobe empfängt. Eine Reihe von Lesebefehlen wird von dem Hostcomputer an den adressierten Speicherchip gesendet, der durch Senden der normalen Umschaltung reagiert. Die zeitliche Abstimmung des Empfangens der normalen Umschaltung, die von dem Hostcomputerchip empfangen wird, wird so lange angepasst, bis die normale Umschaltung ordnungsgemäß empfangen wird.
Abstract:
Ein Verfahren und eine Vorrichtung zum Ermitteln der ordnungsgemäßen zeitlichen Abstimmung für das Empfangen einer von einem adressierten Speicherchip auf einem bidirektionalen Data Strobe gesendeten normalen Umschaltung in einem Hostcomputer in einem Speichersystem. Es wird eine Verschiebung in dem Data Strobe hergestellt, entweder durch Ausgabe des Befehls an den adressierten Speicherchip während eines Einarbeitungszeitraums, den Data Strobe in einen bekannten Zustand zu bringen, oder durch Bereitstellen einer Spannungsverschiebung zwischen einer wahren und einer komplementären Phase in dem Data Strobe oder durch Bereitstellen einer Schaltkreisvorspannung in einem Differenzempfänger auf dem Hostcomputer, der das Data Strobe empfängt. Eine Reihe von Lesebefehlen wird von dem Hostcomputer an den adressierten Speicherchip gesendet, der durch Senden der normalen Umschaltung reagiert. Die zeitliche Abstimmung des Empfangens der normalen Umschaltung, die von dem Hostcomputerchip empfangen wird, wird so lange angepasst, bis die normale Umschaltung ordnungsgemäß empfangen wird.