公开(公告)号：SG68635A1

公开(公告)日：1999-11-16

申请号：SG1997003565

申请日：1997-09-25

Applicant: IBM

Inventor： BALASUBRAMANYAM KARANAM ,  BRODSKY STEPHEN BRUCE ,  CONTI RICHARD ANTHONY ,  EL-KAREH BADIH

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/43 ,  H01L29/78

Abstract: A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

公开(公告)号：DE3763608D1

公开(公告)日：1990-08-16

申请号：DE3763608

申请日：1987-02-17

Applicant: IBM

Inventor： EL-KAREH BADIH ,  GARNACHE RICHARD RAYMOND ,  GHATALIA ASHWIN KANTILAL

IPC: H01L21/76 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/082 ,  H01L21/31 ,  H01L27/10 ,  H01L21/312

Abstract: A method is provided for making a semiconductor structure which includes the steps of forming in a semiconductor body a P/N junction and a first opening (50, 54) in a first insulating layer (42) disposed on the surface of the semiconductor body. A trench (22) is then formed in the semiconductor body having a sidewall located along a given plane through the opening and through the P/N junction. A second layer of insulation (56) is formed within the opening and on the sidewall of the trench. An insulating material (24) is disposed within the trench (22) and over the second insulating layer (56) in the opening and a block (62) or segment of material is located over the trench (22) so as to extend a given distance from the trench over the upper surface of the body. The insulating material (24) and the block (62) are then etched so as to remove the block and the insulating material along the sides of the block. The exposed portions of the second insulating layer (56) are now etched to form a second opening therein within the first opening (50, 54) in the first insulating layer (42). A layer (64) of low viscosity material, such as a photoresist, is formed over the semiconductor body so as to cover the remaining portion of the insulating material (24), the layer (64) of low viscosity material and the insulating material (24) having similar etch rates. The layer (64) of low viscosity material and the insulating material (24) are then simultaneously etched directionally, e.g., by a reactive ion etching process (RIE), until all of the layer (64) of low viscosity material is removed to at least the surface of the second insulating layer (56) at the trench (22). Any suitable wet etchant may then be used, if desired, to remove any remaining low viscosity material disposed within the second opening in the second insulating layer. Metallic contacts (WT, WB, BO) may now be formed, e.g., by evaporation, on the surface of the semiconductor body within the second opening in the second insulating layer without the concern that the metallic material will seep or enter into the trench causing a short at the P/N junction. … In a preferred embodiment of the invention, the insulating material (24) is polyimide and the block (62) of material, as well as the layer (64) of low viscosity material, is made of photoresist.