公开(公告)号：EP0771022A3

公开(公告)日：1998-08-12

申请号：EP96306961

申请日：1996-09-25

Applicant: IBM

Inventor： BRABAZON TERRY J ,  EL-KAREH BADIH ,  MARTIN STUART R ,  RUTTEN MATTHEW JEREMY ,  KAANTA CARTER WELLING

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/3205

CPC classification number: H01L28/40 ,  H01L21/76895

Abstract: A precision analog metal-metal capacitor is fabricated by forming a first capacitor plate (16) in an insulation layer (12) by forming a trench therein, depositing metal within the trench and planarizing the device. A thin dielectric layer (18) is then deposited and patterned over the first capacitor plate (16). A second insulator (20) is then deposited over the device and discrete openings etched therein to expose the insulation layer (18) and first metal plate (16). Metal is deposited within the openings and planarized, thereby forming a contact (26) to the first metal plate (16) and the second metal plate (24) of the capacitor.

公开(公告)号：JPH11317459A

公开(公告)日：1999-11-16

申请号：JP2115999

申请日：1999-01-29

Applicant: IBM

Inventor： BRONNER GARY BELA ,  EL-KAREH BADIH ,  SCHUSTER STANLEY EVERETT

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a dual-gate oxide which is capable of manufacturing a single integrated circuit chip, wherein a logic circuit and a DRAM are combined and manufacturing a field effect transistor(FET) having a dual work function. SOLUTION: First, a thick gate oxide layer 104 is formed on a wafer, than a doped polysilicon layer 106, a silicide tungsten layer 108 and a nitride layer 110 are successively laminated on the oxide layer in order to form a gate stack. A part of the stack is selectively removed, and the wafer on which the logic circuits are formed in re-exposed. A thin gate oxide layer 116 is formed on the re-exposed region of the wafer, a polysilicon gate 120 is formed thereon, and a thick oxide NFET and PFET are formed on the gate. A thick oxide device region is selectively changed into a silicide 146, then the gate is etched from the stack in the thick oxide device region. Finally, dopant ions are implanted into source/drain regions 140 and 142 of the thick gate oxide device and are made to diffuse, and a deep junction and a dual work function gate are formed.

公开(公告)号：JPH10125858A

公开(公告)日：1998-05-15

申请号：JP27582697

申请日：1997-10-08

Applicant: IBM ,  TOSHIBA CORP

Inventor： EL-KAREH BADIH ,  RYAN JAMES GARDNER ,  TANIMOTO KOKICHI

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/092 ,  H01L29/47 ,  H01L29/872

Abstract: PROBLEM TO BE SOLVED: To reduce the latch up incidence of an ESD structure by suppressing the injection of minority carriers in one or both parasitic bipolar transistors, components unique to the ESD structure. SOLUTION: An ESD structure 300 has some semiconductor diffused regions substituted by contacts 316, 320, 328 which form Schottky barrier diodes with underlying semiconductor diffused regions. The Schottky barrier diode is a majority carrier device with a few of minority carriers when being forward biased. This suppresses the possible bipolar operation from bringing up the latch up in the ESD structure. Since the SDB is a majority carrier device, a very few of minority carrier will be injected when the SBD is forward biased, thus preventing the latch up.

公开(公告)号：JPH1056063A

公开(公告)日：1998-02-24

申请号：JP12113097

申请日：1997-05-12

Applicant: IBM

Inventor： RYAN JAMES E ,  EL-KAREH BADIH

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To enhance the resistance against metal migration, by providing the constitution wherein a mutual connecting part and a capacitor include a first metal layer, a dielectric layer, and a second metal layer, and the connecting part of the mutual connecting part to the first metal layer and the second metal 11 layer and the connecting part of the capacitor to the first metal layer and the second metal layer are further included. SOLUTION: The formation of metal studs 32, 33 and 34 is performed at the same time as the pattern formation of a dielectric substance between levels. Then, the metal studs 32 and 33 are connected to only one of layers 17 and 15, respectively, so as to obtain a precision metal-metal capacitor. The stud 32 is connected to only an upper plate 22 and arranged at an arbitrary point upper than the capacitor. The stud 33 should come into contact with only a lower capacitor plate 21 from the upper side. Therefore, the position of the stud 33 is important in comparison with the above described two capacitors. Furthermore, the metal stud 34 in correspondence with the end terminal of the mutual connecting part is in contact with both layers 24 and 25 of the mutual connecting part.

公开(公告)号：DE3572259D1

公开(公告)日：1989-09-14

申请号：DE3572259

申请日：1985-05-29

Applicant: IBM

Inventor： CADE PAUL E ,  EL-KAREH BADIH ,  KIM ICK W

IPC: H01L21/02 ,  H01L21/58 ,  H01L21/74 ,  H01L21/762 ,  H01L21/84 ,  H01L23/58 ,  H01L27/00 ,  H01L27/12 ,  H01L23/56 ,  H01L21/76

Abstract: A method for fabrication of a buried field shield (64) in a semiconductor substrate. A seed substrate is prepared by depositing an epitaxial layer (54) onto a seed wafer (80) and then depositing a heavily doped layer (56) and a thin dielectric (58). The thin dielectric is patterned for contact holes and then a conductive field shield (64) is deposited and patterned. A thick quartz layer (66) is deposited over the field shield and dielectric. A mechanical substrate (68) is anodically bonded to the quartz (66) of the seed substrate and the original seed wafer (80) is etched back to expose the epitaxial layer (54) for further fabrication of integrated electronic devices therein.

公开(公告)号：DE3071521D1

公开(公告)日：1986-05-07

申请号：DE3071521

申请日：1980-09-25

Applicant: IBM

Inventor： EL-KAREH BADIH

IPC: H01L29/73 ,  G11C11/404 ,  H01L21/316 ,  H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/763 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10 ,  H01L27/102 ,  G11C11/24

公开(公告)号：DE2861220D1

公开(公告)日：1981-12-24

申请号：DE2861220

申请日：1978-12-09

Applicant: IBM

Inventor： EL-KAREH BADIH ,  GERSBACH EDWIN JOHN ,  HOUGHTON JAMES RUSSELL

IPC: G11C11/405 ,  G11C11/39 ,  G11C11/403 ,  H01L21/8229 ,  H01L27/07 ,  H01L27/102 ,  G11C11/24 ,  G11C11/34 ,  H01L27/06

Abstract: This describes a novel bipolar dynamic cell especially useful as a Random Access Memory Cell. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell thereby obtaining greater contrast between 0 and 1 signals than can be obtained in prior art cells. This cell is especially useful in memory arrays.

公开(公告)号：MY126357A

公开(公告)日：2006-09-29

申请号：MYPI9705548

申请日：1997-11-19

Applicant: IBM

Inventor： NOBLE WENDLE P ,  GHATALIA ASHWIN K ,  EL-KAREH BADIH

IPC: H01L21/08 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8232 ,  H01L27/08 ,  H01L29/00 ,  H01L29/76 ,  H01L29/78

Abstract: A SEMICONDUCTOR STRUCTURE COMPRISING A TRANSISTOR (39, 139) HAVING A GATE CONDUCTOR (16, 116) THAT HAS FIRST AND SECOND EDGES BOUNDED BY RAISED ISOLATION STRUCTURES (30) (E.G. STI).A SOURCE DIFFUSION IS SELF-ALIGNED TO THE THIRD EDGE AND A DRAIN DIFFUSION IS SELF-ALIGNED TO THE FOURTH EDGE OF THE GATE ELECTRODE.(FIG 8)

公开(公告)号：MY118598A

公开(公告)日：2004-12-31

申请号：MYPI9804916

申请日：1998-10-28

Applicant: IBM

Inventor： BRONNER GARY BELA ,  EL-KAREH BADIH ,  SCHUSTER STANLEY EVERETT

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

Abstract: A METHOD OF FORMING INTEGRATED CIRCUIT CHIPS INCLUDING TWO DISSIMILAR TYPE NFETS AND/OR TWO DISSIMILAR TYPE PFETS ON THE SAME CHIP, SUCH AS BOTH THICK AND THIN GATE OXIDE FETS. A DRAM ARRAY MAY BE CONSTRUCTED OF THE THICK OXIDE FETS AND LOGIC CIRCUITS MAY BE CONSTRUCTED OF THE THIN OXIDE FETS ON THE SAME CHIP. FIRST, A GATE STACK (100) INCLUDING A FIRST, THICK GATE SIO21AYER (104) IS FORMED ON A WAFER. THE STACK INCLUDES A DOPED POLYSILICON LAYER (106) ON THE GATE OXIDE LAYER, A SILICIDE LAYER (108) ON THE POLYSILICON LAYER AND A NITRIDE LAYER (110) ON THE SILICIDE LAYER. PART OF THE STACK IS SELECTIVELY REMOVED TO RE-EXPOSE THE WAFER WHERE LOGIC CIRCUITS ARE TO BE FORMED. A THINNER GATE OXIDE LAYER (116) IS FORMED ON THE RE-EXPOSED WAFER. NEXT, GATES ARE FORMED ON THE THINNER GATE OXIDE LAYER AND THIN OXIDE NFETS AND PFETS ARE FORMED AT THE GATES. AFTER SELECTIVELY SILICIDING THIN OXIDE DEVICE REGIONS, GATES ARE ETCHED FROM THE STACK IN THE THICK OXIDE DEVICE REGIONS. FINALLY, SOURCE AND DRAIN REGIONS (140, 142) ARE IMPLANTED AND DIFFUSED FOR THE THICK GATE OXIDE DEVICES.(FIG. 7)

公开(公告)号：SG70150A1

公开(公告)日：2000-01-25

申请号：SG1999000336

申请日：1999-02-03

Applicant: IBM

Inventor： BRONNER GARY BELA ,  EL-KAREH BADIH ,  SCHUSTER STANLEY EVERETT

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

Abstract: A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.