公开(公告)号：JP2000315777A

公开(公告)日：2000-11-14

申请号：JP2000116633

申请日：2000-04-18

Applicant: IBM

Inventor： GARY B BRONER ,  GAMBINO JEFFREY P ,  KAARU JIEI RADENSU

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce a circuit size and improve manufacturing efficiency by using a capacitor contact for forming a bit-line trench and by forming a conductive bit line that is electrically connected to a field effect transistor in the trench. SOLUTION: A capacitor 100 is fully insulated from a bit line 60 by a dielectric material 80, and the electrical short-circuiting between the bit line 60 and the capacitor 100 is prevented. Further, a capacitor contact 31 is fully insulated from the bit line 60 similarly by an insulation spacer 41. Further, since the spacer 41 is formed in an opening 40 for the bit line 60, the capacitor contact 31 cannot become smaller. Therefore, the capacitor contact 31 with higher importance retains its size and the bit line 60 with lower importance becomes somewhat smaller, thus manufacturing smaller stack structure and hence higher- density integrated circuit device.

公开(公告)号：JP2011023719A

公开(公告)日：2011-02-03

申请号：JP2010157590

申请日：2010-07-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAUBENSPECK TIMOTHY HARRISON ,  GAMBINO JEFFREY P ,  SAUTER WOLFGANG ,  MUZZY CHRISTOPHER DAVID ,  QUESTAD DAVID L ,  SULLIVAN TIMOTHY DOOLING ,  PAUL FORTIER

IPC: H01L21/60

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/03005 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05016 ,  H01L2224/05019 ,  H01L2224/05027 ,  H01L2224/05552 ,  H01L2224/05563 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a structure of a control collapse chip connection (C4) and its manufacturing method, and particularly, a structure to improve reliability of lead-free C4 interconnection and its method. SOLUTION: The structure includes a ball limited metalization (BLM) layer and a solder ball of control collapse chip connection (C4) formed on the BLM layer. Moreover, the structure includes the final metal pad layer under the BLM layer and a cap layer under the final metal pad layer. Then the structure includes an air gap between the final metal pad layer and one of the BLM layer and cap layer under the C4 solder ball. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供控制崩溃芯片连接（C4）的结构及其制造方法，特别是提高无铅C4互连的可靠性的结构及其方法。 解决方案：该结构包括在BLM层上形成的球限制金属化（BLM）层和控制崩溃芯片连接（C4）的焊球。 此外，该结构包括在BLM层下面的最终金属焊盘层和在最终金属焊盘层下面的覆盖层。 然后，该结构在最终金属焊盘层与C4焊球之下的BLM层和盖层之一之间包括气隙。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010157698A

公开(公告)日：2010-07-15

申请号：JP2009267454

申请日：2009-11-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GAMBINO JEFFREY P ,  DAUBENSPECK TIMOTHY HARRISON ,  SULLIVAN TIMOTHY DOOLING ,  SAUTER WOLFGANG ,  MUZZY CHRISTOPHER DAVID

IPC: H01L21/60 ,  H01L21/3205 ,  H01L23/52

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05644 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: PROBLEM TO BE SOLVED: To provide structures with improved solder bump connections and methods of fabricating such structures. SOLUTION: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供具有改进的焊料凸块连接的结构和制造这种结构的方法。 解决方案：本文提供了具有改善的焊料凸点连接的结构和制造这种结构的方法。 该结构包括在电介质层中形成的通孔，以露出形成在通孔中和电介质层上的接触焊盘和捕获焊盘。 捕获垫在电介质层上具有开口以形成分段特征。 焊料凸块沉积在捕获垫上并且在介电层上沉积开口。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH11265985A

公开(公告)日：1999-09-28

申请号：JP10499

申请日：1999-01-04

Applicant: IBM

Inventor： BRONNER GARY B ,  GAMBINO JEFFREY P ,  KOTECKI DAVID E

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming the patterned metal electrode when the metal itself is hard to etch. SOLUTION: The pattern of the metal than is hard to etch is formed by converting the metal that is hard to etch into a plurality of metal components that can be etched in the region, wherein the metal than is hard to etch is removed. This method includes the step, which attaches a metal layer 8 that is hard to etch on a sacrifice metal composition layer 7 and an exposed region, the step, which forms a plurality of metal compositions that can be etched by the reaction of the sacrifice metal composition layer 7 and the metal 8 that is hard to etch, and the step, which selectively removes the plurality of the metal compositions that can be etched and makes to remain the patterned metal layer that is hard to etch on the surface.

公开(公告)号：JPH10214965A

公开(公告)日：1998-08-11

申请号：JP855498

申请日：1998-01-20

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  GARRY BELLA BRONNER ,  MANDELMAN JACK ALLAN ,  NESBIT LARRY A

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234

Abstract: PROBLEM TO BE SOLVED: To adjust the threshold voltage at the corner of a device without requiring any additional mask by doping the central part of a channel region at some concentration and doping a channel region adjacent to a corner region at a higher concentration. SOLUTION: N type (arsenic) dopant ions 19 are implanted compensatingly. The compensatory implantation is performed in order to compensate for the threshold voltage implantation at the part of the side wall of STI trench structures 18a-18c contiguous to the corner of a substrate 12 other than the corner region 25 and to suppress the effect of P-type ion implantation 21 in the channel region onto the following stage by means of N type doping ions 19 so that the corner region 25 has a higher doping concentration after boron B doping stage. A spacer 16 prevents the compensatory implantation at the corner of the device except the central channel regions 20a, 20b, 20c and 20d.

公开(公告)号：WO2009140099A3

公开(公告)日：2010-01-21

申请号：PCT/US2009042766

申请日：2009-05-05

Applicant: IBM ,  ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

Inventor： ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

IPC: H01L31/112

CPC classification number: H01L27/14685 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14689 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

Abstract translation: 具有小于由光电二极管（8）可检测的光的波长范围的垂直（h）和横向（p）尺寸的凸起（5）形成在具有不同折射率的两个层之间的光学界面处。 突起可以通过使用在第二聚合物嵌段组分（111）的基体内形成第一聚合物嵌段组分（112）的亚光刻特征阵列的自组装嵌段共聚物来形成。 聚合物嵌段组分的图案被转移到第一光学层（4）中以形成纳米级突起的阵列。 或者，可以使用常规光刻来形成尺寸小于光的波长的突起。 第二光学层直接形成在第一光学层的突起上。 第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

公开(公告)号：WO2007127816A2

公开(公告)日：2007-11-08

申请号：PCT/US2007067449

申请日：2007-04-26

Applicant: IBM ,  FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

Inventor： FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads 37 with ball limiting metallization on an integrated circuit chip 30 by using a damascene process and preferably Cu metallization 32 in the chip 30 and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad 52 is formed in the top insulating layer 51 and it also serves as the final level of metallization in the chip.

Abstract translation: 一种用于在集成电路芯片30上通过使用镶嵌工艺，优选在芯片30中的铜金属化层32以及用于兼容性的球限制金属化中，优选地形成具有球限制金属化的Pb-铅C4连接或俘获垫37的方法。 在两个实施例中，捕获垫52形成在顶部绝缘层51中，并且还用作芯片中的最终金属化水平。

公开(公告)号：WO2006071540A3

公开(公告)日：2007-04-12

申请号：PCT/US2005045328

申请日：2005-12-14

Applicant: IBM ,  ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

IPC: H01L29/04

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

Abstract: An image sensor (20) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (135a, 135b) allowing for incorporation of a thinner interlevel dielectric stack (130a-130c) to result in a pixel array (100) exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal (132a, 132b) that traverses the optical path of each pixel in the sensor array or, that have portions (50) of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer (142) may be formed atop the Cu metallization by a self-aligned deposition.

Abstract translation: 一种图像传感器（20）及其制造方法，其中传感器包括铜（Cu）金属化水平（135a，135b），允许结合更薄的层间电介质堆叠（130a-130c）以产生呈现增加的像素阵列（100） 光敏感。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属（132a，132b）的最小厚度的结构，或者具有从每个的光路中选择性地去除的阻挡层金属的部分（50） 像素，从而最小化反射率。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层（142）可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：WO2011163429A3

公开(公告)日：2012-02-23

申请号：PCT/US2011041546

申请日：2011-06-23

Applicant: IBM ,  GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

IPC: H01L21/02 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L28/55 ,  H01L27/11507

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator (18) layer of a CMOS structure (10). The method further includes forming a top plate (32) and a bottom plate (28) over the barrier layer. The method further includes forming a ferro-electric material (30) between the top plate (32) and the bottom plate (28). The method further includes encapsulating the barrier layer, top plate (32), bottom plate (28) and ferro-electric material (30) with an encapsulating material (36). The method further includes forming contacts (20,44a) to the top plate (32) and bottom plate (28), through the encapsulating material (36). At least the contact (44a) to the top plate (32) and a contact (20) to a diffusion of the CMOS structure are in electrical connection through a common wire.

Abstract translation: 铁电电容器模块，制造方法和设计结构。 制造铁电电容器的方法包括在CMOS结构（10）的绝缘体（18）层上形成阻挡层。 该方法还包括在阻挡层上形成顶板（32）和底板（28）。 该方法还包括在顶板（32）和底板（28）之间形成铁电材料（30）。 该方法还包括用封装材料（36）封装阻挡层，顶板（32），底板（28）和铁电材料（30）。 该方法还包括通过封装材料（36）将接触件（20,44a）形成到顶板（32）和底板（28）。 至少到顶板（32）的接触（44a）和与CMOS结构的扩散的接触（20）通过公共电线电连接。