公开(公告)号：JP2000164697A

公开(公告)日：2000-06-16

申请号：JP33676599

申请日：1999-11-26

Applicant: IBM ,  SIEMENS AG

Inventor： GARY B BRONER ,  COSTRINI GREG ,  RADENS CARL J ,  RAYNER E SCHNABEL

IPC: H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To achieve low capacitance and low resistance by simultaneously performing the pattern formation of a via and a grooved line in an interlayer dielectric, by simultaneously etching the via and the grooved line, and by simultaneously filling the via and the grooved line with metal. SOLUTION: On a substrate, desired linear features and vertical interconnection are formed (S700). A grooved line and a via are simultaneously etched (S701). A metallization layer is subjected pattern formation by lithography, and is etched by RIE or the like (S702). The via and the grooved line are filled by the same metallization process (S703). The filled via and the grooved line are finished by one-time common etching or polishing process so that a structure has a flat and uniform upper surface (S704). As a result, both of low-capacitance and low-resistance metallization can be formed.

公开(公告)号：JP2001077321A

公开(公告)日：2001-03-23

申请号：JP2000220495

申请日：2000-07-21

Applicant: IBM

Inventor： GARY B BRONER ,  GAMBINO JEFFREY PETER ,  RADENS CARL J

IPC: B24B37/04 ,  H01L21/027 ,  H01L21/28 ,  H01L21/304 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To realize a process for manufacturing two kinds of different gate dielectric thicknesses by using a polysilicon mask and chemical mechanical polishing(CMP). SOLUTION: A thick gate dielectric 102 is grown on a substrate having a memory array area 201 and a logical device area 101, and a gate stack containing a first polysilicon layer 103 is formed on the dielectric 102. Then a thin gate dielectric 200 is formed on the substrate above the logical device area 101, and a second polysilicon layer 300 is formed in the logical device area 101. The thickness of the second polysilicon layer 300 is at least made to be equal to that of the gate stack in the memory array area 201. The structure is flattened by using chemical mechanical polishing(CMP), and the gate stack in the memory array area 201 and logical device area 101 is patterned.

公开(公告)号：JP2000315777A

公开(公告)日：2000-11-14

申请号：JP2000116633

申请日：2000-04-18

Applicant: IBM

Inventor： GARY B BRONER ,  GAMBINO JEFFREY P ,  KAARU JIEI RADENSU

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce a circuit size and improve manufacturing efficiency by using a capacitor contact for forming a bit-line trench and by forming a conductive bit line that is electrically connected to a field effect transistor in the trench. SOLUTION: A capacitor 100 is fully insulated from a bit line 60 by a dielectric material 80, and the electrical short-circuiting between the bit line 60 and the capacitor 100 is prevented. Further, a capacitor contact 31 is fully insulated from the bit line 60 similarly by an insulation spacer 41. Further, since the spacer 41 is formed in an opening 40 for the bit line 60, the capacitor contact 31 cannot become smaller. Therefore, the capacitor contact 31 with higher importance retains its size and the bit line 60 with lower importance becomes somewhat smaller, thus manufacturing smaller stack structure and hence higher- density integrated circuit device.