公开(公告)号：JPH1056000A

公开(公告)日：1998-02-24

申请号：JP14674097

申请日：1997-06-04

Applicant: IBM

Inventor： KAARU JIEI RADENSU ,  SHINSHIA EI FUEACHIYOKU ,  REEPIN RII ,  RICHIYAADO MAASU RUJIERO ,  UIRIAMU JIYOOZEFU SUROBUITSU

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/60

Abstract: PROBLEM TO BE SOLVED: To use a device, having a nitride silicon etch-stop layer, by supplying a gas etching agent mixture containing C4 F8 , CO and inert gas in the ratio in a specified range. SOLUTION: A gate stack 10 is etched, and a side wall 13 of the gate stack 10 obtained as a result is oxidized for sticking a thin silicon nitride liner 14. Then phosphorus glass silicate is laminated by low pressure chemical vapor phase sticking, etc., as an upper layer 15 of the oxide. Then the upper layer 15 is flattened by mechanochemical polishing, etc., to form a borderless contact pattern. And the oxide upper layer 15 is dry-etched for the nitride liner 14. At this time, a gas etching agent mixture containing 0.5-5% of C4 F8 , 0-78% of CO and 18-97% of inert gas is supplied. So that a device having a silicon nitride etch-stop layer can be used.

公开(公告)号：JP2000315777A

公开(公告)日：2000-11-14

申请号：JP2000116633

申请日：2000-04-18

Applicant: IBM

Inventor： GARY B BRONER ,  GAMBINO JEFFREY P ,  KAARU JIEI RADENSU

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce a circuit size and improve manufacturing efficiency by using a capacitor contact for forming a bit-line trench and by forming a conductive bit line that is electrically connected to a field effect transistor in the trench. SOLUTION: A capacitor 100 is fully insulated from a bit line 60 by a dielectric material 80, and the electrical short-circuiting between the bit line 60 and the capacitor 100 is prevented. Further, a capacitor contact 31 is fully insulated from the bit line 60 similarly by an insulation spacer 41. Further, since the spacer 41 is formed in an opening 40 for the bit line 60, the capacitor contact 31 cannot become smaller. Therefore, the capacitor contact 31 with higher importance retains its size and the bit line 60 with lower importance becomes somewhat smaller, thus manufacturing smaller stack structure and hence higher- density integrated circuit device.

公开(公告)号：JP2002026147A

公开(公告)日：2002-01-25

申请号：JP2001189079

申请日：2001-06-22

Applicant: IBM

Inventor： MANDELMAN JACK A ,  RAMACHANDORA DEIVAKARUNI ,  KAARU JIEI RADENSU ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure including a planar semiconductor substrate. SOLUTION: The semiconductor substrate has a deep trench. The deep trench has side walls and one bottom part. A storage capacitor is located at the bottom of the deep trench. On at least one sidewall of the deep trench, a vertical transistor extends downwardly. This transistor has source diffusion extending in the plane of the substrate adjacent to the deep trench. On at least the other sidewall of the deep trench on the opposite side from the vertical transistor, a separation part extends downwardly. A shallow trench separation area extends laterally to the sidewall, where the vertical transistor extends along the surface of the substrate. In the inside of the deep trench, a gate conductor extends. A word line extends onto the deep trench and is connected to the gate conductor. The bit line extends onto the surface of the substrate and has a contact for the source diffusion between shallow trench separation areas.

公开(公告)号：JP2000022101A

公开(公告)日：2000-01-21

申请号：JP15133899

申请日：1999-05-31

Applicant: IBM ,  SIEMENS AG

Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  KAARU JIEI RADENSU

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce remarkably the distributed series resistance of trench electrodes, by manufacturing trench capacitors using a method of forming heat- resistant metallic salicide materials on the trench regions having low trench capacitors. SOLUTION: A narrow upper region 16a and a wide lower region 16b are filled with ploysilicon layers 26 and the polysilicon layers 26 are planarized. Next, the polysilicon layers 26 are recessed, then conformal heat-resistant metallic layers 30 are adhered. After that, the salicide is formed at the interface between the heat-resistant metal in the region 16b and the polysilicon by annealing. As a result, a heat-resistant metallic salicide layer 32 is formed in the wide lower trench region 16b. It is preferable that the heat-resistant metallic salicide layer is not formed in the narrow upper trench region 16b. Next, the heat-resistant metallic layer 30 remained in the upper layer 16a is removed. Then, the additional polysilicon is filled in the trench. After that, the capacitor structure is planarized.

公开(公告)号：JP2000252364A

公开(公告)日：2000-09-14

申请号：JP2000047093

申请日：2000-02-24

Applicant: IBM ,  SIEMENS AG

Inventor： BRINTZINGER AXEL ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  KAARU JIEI RADENSU

IPC: H01L21/82 ,  G11C29/04 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/02 ,  H01L27/108 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a fuse link structure which reduces the magnitude of damage which is caused when a fuse element is blown and to provide its method. SOLUTION: This integrated circuit is provided with a main element 102. The integrated circuit is provided with a redundant element 104 which is replaced selectively with the main element 102 by at lease one fuse. The fuse contains a first layer 401 which comprises at least one fuse link region 402, contains a second layer 401 on the first layer, a gap 410 inside the second layer on the fuse link region 402, and contains a fuse window 408 in a dielectric layer 407. Since the gap 410 guides energy and a fuse material to the fuse window 408 from the fuse link region 402, it is possible to reduce damage to a circumferential structure.

公开(公告)号：JP2000082800A

公开(公告)日：2000-03-21

申请号：JP22931499

申请日：1999-08-13

Applicant: IBM ,  SIEMENS AG

Inventor： BRONNER GARY B ,  KAARU JIEI RADENSU ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To form a buried strap through a simplified process by a structure wherein the part of second conductive material positioned between the depth of a strap and the upper surface of a trench includes a buried strap. SOLUTION: The method for forming a strap comprises a step for making a trench 200 in a substrate 201, a step for filling the trench 200 partially with a first conductive material 202, and a step for applying a color material 203 to the part of the trench 200 on the first conductive material 202. The method further comprises a step for etching the color material 203 down to the depth of a strap 205 beneath the upper surface of the trench 200, and a step for filling the trench 200 with a second conductive material 210. The part of second conductive material 210 positioned between the depth of the strap 205 and the upper surface of the trench 200 is formed while including the buried strap. 205.