公开(公告)号：DE2453528A1

公开(公告)日：1975-07-10

申请号：DE2453528

申请日：1974-11-12

Applicant: IBM

Inventor： BAKER THEODORE HARRIS ,  GHAFGHAICHI MAJID

IPC: H05K3/46 ,  H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/3213

Abstract: In the fabrication of integrated circuits, a method of forming openings through an insulative layer wherein a plurality of openings being formed through said insulative layer are subjected to two separate etching steps in order to insure that the opening is made.

公开(公告)号：DE1961493A1

公开(公告)日：1970-07-09

申请号：DE1961493

申请日：1969-12-08

Applicant: IBM

Inventor： GHAFGHAICHI MAJID

IPC: G01R29/02 ,  G01R31/26 ,  G01R31/22

Abstract: Method and apparatus for characterizing the dynamic input impedance of a test element by measuring the rise-time degradation of an input waveform. A pulse having a very fast rise-time is supplied by a pulse generator and transmitted down two branches of a balanced transmission line. One leg of the balanced transmission line is connected to a sensing means while the other leg of the balanced transmission line is connected to a test element as well as the sensing means. Thus, the sensing means would receive two identical pulses but for the rise-time degradation of the pulse connected to the test element. The test element is characterized on the basis of this rise-time degradation.

公开(公告)号：DE2963058D1

公开(公告)日：1982-07-29

申请号：DE2963058

申请日：1979-04-24

Applicant: IBM

Inventor： BALYOZ JOHN ,  CHANG CHI SHIH ,  FOX BARRY CHARLES ,  GHAFGHAICHI MAJID ,  JEN TEH-SEN ,  MOONEY DONALD BLAISE ,  PALMIERI JOHN ALDO

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L27/02

Abstract: Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices. In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.

公开(公告)号：DE2860169D1

公开(公告)日：1980-12-18

申请号：DE2860169

申请日：1978-07-27

Applicant: IBM

Inventor： DALAL HORMAZDYAR MINOCHER ,  GHAFGHAICHI MAJID ,  KASPRZAK LUCIAN ALEXANDER ,  WIMPFHEIMER HANS

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L21/60 ,  H01L23/532 ,  H01L29/43 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872 ,  H01L29/40 ,  H01L23/48

Abstract: A silicon semiconductor device having contacts which include tantalum. The tantalum is useful in particular for fabricating Schottky barrier diodes having a low barrier height. The method includes: precleaning the silicon substrate prior to depositing the tantalum; depositing the tantalum at low pressure and low substrate temperature to avoid oxidation of the tantalum; and sintering the contact to reduce any interfacial charges and films remaining between the silicon and tantalum. When a metal which reacts with silicon during processing, such as aluminum, is used as interconnection metallurgy, a layer of chrome must be deposited between the tantalum and aluminum.

公开(公告)号：CA961168A

公开(公告)日：1975-01-14

申请号：CA138127

申请日：1972-03-27

Applicant: IBM

Inventor： GHAFGHAICHI MAJID ,  TUMAN DANIEL

IPC: H01L27/08

Abstract: Diffused impedance regions are precisely tuned by tailoring electrically interconnected circuitous epitaxial channels.

公开(公告)号：DE2243809A1

公开(公告)日：1973-05-10

申请号：DE2243809

申请日：1972-09-07

Applicant: IBM

Inventor： BAKER THEODORE HARRIS ,  GHAFGHAICHI MAJID ,  TOTTA PAUL ANTHONY

IPC: H05K13/02 ,  H01L21/02 ,  H01L21/60 ,  H01L21/822 ,  H01L23/00 ,  H01L27/04 ,  H01L7/34

Abstract: 1393423 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 12 Sept 1972 [3 Nov 1971] 42279/72 Heading H1K Damage to the surface of a semi-conductor chip 21 due to impact by the edges and corners of other similar chips such as 22 during handling is reduced by arranging a plurality of suitably situated and dimensioned projections on the chip surface. Some of the projections 19 may be contact pads, and additional projections 18 may also be provided having the same height and composition (e.g. a solder bump on a Cr/Cu/ Au layer) on the contact pads 19. Preferably at least 75% of the chip surface area is protected against impact in this way, protection not being necessary in certain regions of the surface where circuit function would not be impaired by the effects of chip impacts.