公开(公告)号：DE3782500T2

公开(公告)日：1993-05-06

申请号：DE3782500

申请日：1987-12-23

Applicant: IBM

Inventor： GLAISE RENE ,  HARTMANN YVES ,  HUON PIERRE ,  PEYRONNENC MICHEL

IPC: G06F13/16 ,  G06F13/18 ,  G06F13/42

Abstract: The memory interface mechanism according to the invention is driven from the memory controller side. It comprises lines which are shared by the memory user devices 1 and 2 and lines which are specific to the memory user devices. The shared lines are the address and data bus lines 20,22, the byte select lines 24 the data and address clock lines 26 and 24 and the last operation line 30. The specific lines are request lines 11 and 12, address user indicator and data user indicator lines 15,17;16,18. A user initiates a memory operation by activating its request line, then it waits for the activation by the memory interface control circuit 5 for the activation of the address and data user indicator lines 15 and 17. The user controls the address and data transfer count and ends the transfer by activating the last operation line 30. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven, which allows to take fully advantage of the page mode facility of the memory. The memory operations may be pipelined since servicing a request from a user may be started before servicing the request from the the previous selected user is ended.

公开(公告)号：DE3482509D1

公开(公告)日：1990-07-19

申请号：DE3482509

申请日：1984-12-28

Applicant: IBM

Inventor： GLAISE RENE

IPC: G06F11/10 ,  G06F12/16 ,  G11C29/00

公开(公告)号：FR2330117A1

公开(公告)日：1977-05-27

申请号：FR7533884

申请日：1975-10-31

Applicant: IBM FRANCE

Inventor： CROISIER ALAIN ,  GLAISE RENE

IPC: G11C27/04 ,  G11C19/18 ,  H01L21/33 ,  H01L21/339 ,  H01L29/70 ,  H01L29/762 ,  H03H11/26 ,  G11C19/28

Abstract: Arrangement allowing an input bucket brigade (BBD) stage to feed several other BBD stages in parallel with no loss of the signal transferred from the input stage to the subsequent ones. An input voltage corresponding to a charge quantity is stored in the second capacitor of the input BBD stage. The drain of the output transistor of the input stage is connected to a first BBD stage wherein the first capacitor is connected to the source electrode of the first transistor of a second BBD stage. The first transistors of both stages are controlled by the same clock pulses. When these transistors are turned on, the capacitors connected thereto are in series with the second capacitor of the input stage. Consequently, the same current will flow through these capacitors, which will thus store the same charges so that the charge representing the input voltage will be reproduced in the first capacitors of the two BBD stages connected to the input stage. Means are provided for grounding the terminal of the first capacitor in the first stage that is connected to the source of the first transistor in the second stage at the time the transfer of the duplicated charge takes place.

公开(公告)号：DE602007008612D1

公开(公告)日：2010-09-30

申请号：DE602007008612

申请日：2007-10-08

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  GLAISE RENE

IPC: H04L1/00 ,  H04L25/03

公开(公告)号：DE3882223T2

公开(公告)日：1994-01-27

申请号：DE3882223

申请日：1988-04-29

Applicant: IBM

Inventor： DEBORD PIERRE ,  GLAISE RENE

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H03M13/19

Abstract: A digital error detection and correction apparatus for correcting n-bit data words comprising a field of n-r data bits and a field of r error-correcting-code-ECC bits according to an error correcting code. The n-bit data words are organized in packages of b bits, and the invention is capable of correcting one package having suffered at least one hard failure and a single soft error being located in a different package. The apparatus of the invention involves an error correcting code which gives a first syndrome when the data word has suffered a first error coming from at least one error in a first package and a single error in a second package different from the first package, which also gives a second syndrôme when the data word has suffered a second error coming from at least one error in the above first package, and a single error in a third package. The error correcting code is such that the equality of the above first and second syndromes results in the equality of the first and second errors. The apparatus of the invention further includes means (24) for storing the syndrome of a first data word v, and means (24) for adding the syndrôme a second data word v min , the latter data word v min being generated from the first data word v by means of an "invert write" and an " invert read" procedure. The above addition allows the masking of the single soft error. The invention further includes means (20) for determining whether the result of the above addition provides a syndrome characterizing a single package syndrôme, in order to determine the number of the package having suffered at least one hard error, and means (21, 22, 50-XX) operative in response to said determination for directly locating the positions of the errors, either soft and hard, in order to restore the originally stored data word.

公开(公告)号：DE3882223D1

公开(公告)日：1993-08-12

申请号：DE3882223

申请日：1988-04-29

Applicant: IBM

Inventor： DEBORD PIERRE ,  GLAISE RENE

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H03M13/19

Abstract: In the digital error detection and correction appts., an error correcting code gives a first syndrome when the data word has suffered an error coming from at least one error in a first package and a single error in a second package. The second package is different from the first package, and the code gives a second syndrome when the data word has suffered a second error coming from at least one error in the first package, and a single error in a third package. The error correcting code is such that the equality of the first and second syndrome results in the equality of the first and second error. The positions of the errors are directly located and the corrected data word is restored.

公开(公告)号：CA1299764C

公开(公告)日：1992-04-28

申请号：CA569055

申请日：1988-06-09

Applicant: IBM

Inventor： GLAISE RENE ,  HARTMANN YVES ,  HUON PIERRE ,  PEYRONNENC MICHEL

IPC: G06F13/16 ,  G06F13/18 ,  G06F13/42

Abstract: FR 9 87 018 EFFICIENT INTERFACE FOR THE MAIN STORE OF A DATA PROCESSING SYSTEM The memory interface mechanism according to the invention is driven from the memory controller side. It comprises lines which are shared by the memory user devices 1 and 2 and lines which are specific to the memory user devices. The shared lines are the address and data bus lines 20,22, the byte select lines 24 the data and address clock lines 26 and 24 and the last operation line 30. The specific lines are request lines 11 and 12, address user indicator and data user indicator lines 15,17;16,18. A user initiates a memory operation by activating its request line, then it waits for the activation by the memory interface control circuit 5 for the activation of the address and data user indicator lines 15 and 17. The user controls the address and data transfer count and ends the transfer by activating the last operation line 30. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven, which allows to take fully advantage of the page mode facility of the memory. The memory operations may be pipelined since servicing a request from a user may be started before servicing the request from the the previous selected user is ended. (Figure 1)

公开(公告)号：CA1091349A

公开(公告)日：1980-12-09

申请号：CA264632

申请日：1976-10-29

Applicant: IBM

Inventor： CROISIER ALAIN ,  GLAISE RENE

IPC: G11C27/04 ,  G11C19/18 ,  H01L21/33 ,  H01L21/339 ,  H01L29/70 ,  H01L29/762 ,  H03H11/26 ,  H03K17/02 ,  H03K17/56

Abstract: DEVICE FOR REPRODUCING THE CHARGE STORED IN AN INPUT CAPACITOR IN A PLURALITY OF OUTPUT CAPACITORS Arrangement allowing an input bucket brigade (BBD) stage to feed several other BBD stages in parallel with no loss of the signal transferred from the input stage to the subsequent ones. An input voltage corresponding to a charge quantity is stored in the second capacitor of the input BBD stage. The drain of the output transistor of the input stage is connected to a first BBD stage wherein the first capacitor is connected to the source electrode of the first transistor of a second BBD stage. The first transistors of both stages are controlled by the same clock pulses. When these transistors are turned on, the capacitors connected thereto are in series with the second capacitor of the input stage. Consequently, the same current will flow through these capacitors, which will thus store the same charges so that the charge representing the input voltage will be reproduced in the first capacitors of the two BBD stages connected to the input stage. Means are provided for grounding the terminal of the first capacitor in the first stage that is connected to the source of the first transistor in the second stage at the time the transfer of the duplicated charge takes place.

公开(公告)号：DE2646830A1

公开(公告)日：1977-05-05

申请号：DE2646830

申请日：1976-10-16

Applicant: IBM

Inventor： CROISIER ALAIN ,  GLAISE RENE

IPC: G11C27/04 ,  G11C19/18 ,  H01L21/33 ,  H01L21/339 ,  H01L29/70 ,  H01L29/762 ,  H03H11/26

Abstract: Arrangement allowing an input bucket brigade (BBD) stage to feed several other BBD stages in parallel with no loss of the signal transferred from the input stage to the subsequent ones. An input voltage corresponding to a charge quantity is stored in the second capacitor of the input BBD stage. The drain of the output transistor of the input stage is connected to a first BBD stage wherein the first capacitor is connected to the source electrode of the first transistor of a second BBD stage. The first transistors of both stages are controlled by the same clock pulses. When these transistors are turned on, the capacitors connected thereto are in series with the second capacitor of the input stage. Consequently, the same current will flow through these capacitors, which will thus store the same charges so that the charge representing the input voltage will be reproduced in the first capacitors of the two BBD stages connected to the input stage. Means are provided for grounding the terminal of the first capacitor in the first stage that is connected to the source of the first transistor in the second stage at the time the transfer of the duplicated charge takes place.