公开(公告)号：PL348253A1

公开(公告)日：2002-05-20

申请号：PL34825399

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F9/48 ,  G06F15/173 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：HU0104536A2

公开(公告)日：2002-03-28

申请号：HU0104536

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  DEBACKER PHILIPPE LOUIS ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F9/48 ,  G06F15/173 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：CZ20012154A3

公开(公告)日：2001-09-12

申请号：CZ20012154

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：MY124353A

公开(公告)日：2006-06-30

申请号：MYPI9903692

申请日：1999-08-26

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  IACHETTA RICHARD NICHOLAS JR

IPC: G06F13/00 ,  G06F15/163 ,  G06F12/08

Abstract: A NON-UNIFORM MEMORY ACCESS (NUMA) DATA PROCESSING SYSTEM (8) INCLUDES A NODE AND SECOND INTERCONNECT (22) TO WHICH AT LEAST A FIRST PROCESSING NODE ARE COUPLED. THE FIRST AND THE SECOND PROCESSING NODES EACH INCLUDES A LOCAL INTERCONNECT (16), A PROCESSOR (12A-12D) COUPLED TO THE LOCAL INTERCONNECT, A SYSTEM MEMORY (18) COUPLED TO THE LOCAL INTERCONNECT, AND A NODE CONTROLLER (20) INTERPOSED BETWEEN THE LOCAL INTERCONNECT AND THE NODE INTERCONNECT. IN ORDER TO REDUCE COMMUNICATION LATENCY, THE NODE CONTROLLER OF THE FIRST PROCESSING NODE SPECULATIVELY TRANSMITS REQUEST TRANSACTIONS RECEIVED FROM THE LOCAL INTERCONNECT OF THE FIRST PROCESSOR NODE TO THE SECOND PROCESSING NODE VIA THE NODE INTERCONNECT.IN ONE EMBODIMENT, THE NODE CONTROLLER OF THE FIRST PROCESSING NODE SUBSEQUENTLY TRANSMITS A STATUS SIGNAL TO THE NODE CONTROLLER OF THE SECOND PROCESSING NODE IN ORDER TO INDICATE HOW THE REQUEST TRANSACTION SHOULD BE PROCESSED AT THE SECOND PROCESSING NODE.FIGURE 1

公开(公告)号：CA2279138C

公开(公告)日：2006-03-21

申请号：CA2279138

申请日：1999-07-29

Applicant: IBM

Inventor： IACHETTA RICHARD NICHOLAS JR ,  CARPENTER GARY DALE ,  GLASCO DAVID BRIAN

IPC: G06F12/02 ,  G06F15/16 ,  G06F12/08

Abstract: A non-uniform memory access (NUMA) computer system includes a node interconnect and a plurality of processing nodes that each contain at least one processor, a local interconnect, a local system memory, and a node controller coupled to both a respective local interconnect and the node interconnect. According to the method of the present invention, a communication transaction is transmitted on the node interconnect from a local processing node to a remot e processing node. In response to receipt of the communication transaction by the remote processin g node, a response including a coherency response field is transmitted on the node interconnect from the remote processing node to the local processing node. In response to receipt of the response at the local processing node, a request is issued on the local interconnect of the local processing node concurrently with a determination of a coherency response indicated by the coherency response field.

公开(公告)号：CA2349662C

公开(公告)日：2003-02-18

申请号：CA2349662

申请日：1999-11-30

Applicant: IBM

Inventor： DEBACKER PHILIPPE LOUIS ,  GLASCO DAVID BRIAN ,  DEAN MARK EDWARD ,  ROCKHOLD RONALD LYNN ,  CARPENTER GARY DALE

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nod es coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs . Although each external interrupt domain typically includes only a single nod e, interrupt channelling or interrupt funnelling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrup ts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system.

公开(公告)号：CA2349662A1

公开(公告)日：2000-06-22

申请号：CA2349662

申请日：1999-11-30

Applicant: IBM

Inventor： ROCKHOLD RONALD LYNN ,  GLASCO DAVID BRIAN ,  DEBACKER PHILIPPE LOUIS ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nod es coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs . Although each external interrupt domain typically includes only a single nod e, interrupt channelling or interrupt funnelling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrup ts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system.