公开(公告)号：GB2509262A

公开(公告)日：2014-06-25

申请号：GB201404141

申请日：2012-09-14

Applicant: IBM

Inventor： CARTIER EDUARD A ,  GREENE BRIAN J ,  GUO DECHAO ,  WANG GAN ,  WANG YANFENG ,  WONG KEITH H

IPC: H01L29/66

Abstract: FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide. A structure comprises a plurality of fin structures patterned from a semiconductor film. The structure further comprises a gate stack wrapping around the plurality of fin structures. The gate stack includes a high-k dielectric material subjected to a lateral oxygen diffusion to induce Vt shift of the gate stack.

公开(公告)号：DE112012003981T5

公开(公告)日：2014-06-18

申请号：DE112012003981

申请日：2012-09-14

Applicant: IBM

Inventor： CARTIER EDUARD A ,  WANG YANFENG ,  WONG KEITH K H ,  GREENE BRIAN J ,  GUO DECHAO ,  WANG GAN

IPC: H01L21/00

Abstract: Es werden FinFET-Strukturen und Verfahren zum Fertigen der FinFET-Strukturen offenbart. Das Verfahren beinhaltet ein Durchführen eines Sauerstofftemperprozesses an einem Gate-Stapel einer FinFET-Struktur, um eine Vt-Verschiebung hervorzurufen. Der Sauerstofftemperprozess wird nach einem Abtragen der Seitenwand und nach einer Silicidierung durchgeführt. Eine Struktur weist eine Vielzahl von Finnenstrukturen auf, die aus einer Halbleiterdünnschicht strukturiert worden sind. Die Struktur weist des Weiteren einen Gate-Stapel auf, der die Vielzahl von Finnenstrukturen umhüllt. Der Gate-Stapel beinhaltet ein dielektrisches High-k-Material, das einer seitlichen Sauerstoffdiffusion unterzogen wird, um eine Vt-Verschiebung des Gate-Stapels hervorzurufen.

公开(公告)号：SG174853A1

公开(公告)日：2011-11-28

申请号：SG2011057296

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

公开(公告)号：SG124361A1

公开(公告)日：2006-08-30

申请号：SG200600196

申请日：2006-01-11

Applicant: CHARTERED SEMICONDUCTOR MFG ,  SAMSUNG ELECTRONICS CO LTD ,  IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MINCHUL SUN ,  JAHUM KU ,  GREENE BRIAN J ,  ELLER MANFRED ,  SUNFEI FANG ,  LENG TAN WEE ,  ZHIJIONG LUO

Abstract: A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.