公开(公告)号：US3755793A

公开(公告)日：1973-08-28

申请号：US3755793D

申请日：1972-04-13

Applicant: IBM

Inventor： HO I ,  MALEY G ,  HWA N YU

IPC: G11C17/00 ,  G11C7/20 ,  G11C11/35 ,  G11C11/404 ,  G11C17/12 ,  H01L27/108 ,  G11C7/00 ,  G11C11/34 ,  H03K25/02

CPC classification number: G11C17/12 ,  G11C7/20 ,  G11C11/35 ,  G11C11/404 ,  H01L27/108

Abstract: A latent image memory is selectively operable as either a readwrite memory or a read-only memory. The memory comprises an array of cells each preferably consisting of a single active device. A first set of the cells are each adapted to store either one of two binary digits. A second set of the cells are each responsive to a first condition for storing either one of two binary digits and responsive to a second condition for storing only a single predetermined binary digit. Means are provided for selecting either the first condition to render the array operable as a read-write memory, or the second condition to render the array operable as a read-only memory. Each of the cells of the first set preferably comprises a field-effect transistor connected to a capacitor, and each of the cells of the second set preferably comprises a charge-coupled device.

Abstract translation: 潜像存储器可选择性地操作为读写存储器或只读存储器。 存储器包括每个优选由单个有源器件组成的单元阵列。 第一组单元适合于存储两个二进制数字之一。 第二组单元各自响应用于存储两个二进制数字中的一个的第一条件，并响应于仅存储单个预定二进制数字的第二条件。 提供了用于选择第一条件以使得阵列可操作为读写存储器的装置，或者用于使阵列可操作为只读存储器的第二条件。 第一组的每个单元优选地包括连接到电容器的场效应晶体管，并且第二组的每个单元优选地包括电荷耦合器件。

公开(公告)号：US3740723A

公开(公告)日：1973-06-19

申请号：US3740723D

申请日：1970-12-28

Applicant: IBM

Inventor： BEAUSOLEIL W ,  HO I ,  PRICER W

IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00 ,  G11C9/00 ,  G11C11/34

CPC classification number: G11C19/00 ,  G06F12/0864 ,  G11C11/415

Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.

公开(公告)号：US3735358A

公开(公告)日：1973-05-22

申请号：US3735358D

申请日：1970-12-31

Applicant: IBM

Inventor： HO I

IPC: G11C17/08 ,  H01L27/102 ,  H03K19/086 ,  G11C11/40 ,  G11C17/00

CPC classification number: H03K19/086 ,  G11C17/08 ,  H01L27/1024

Abstract: A read only memory comprising a plurality of semiconductor device cells arranged in rows and columns. Spaced conductive lines extending in a Y direction are connected to a first cell terminal. A plurality of second cell terminals defining a row or column are selectively interconnected to one or the other of a pair of adjacent X lines. The semiconductor device cells interconnected between the adjacent X line pair are responsive to digital input signals applied on the plurality of Y lines to generate distinct logical signals on the pair of adjacent X lines.

Abstract translation: 一种只读存储器，包括以行和列排列的多个半导体器件单元。 沿Y方向延伸的间隔导线连接到第一单元端子。 限定行或列的多个第二单元端子选择性地互连到一对相邻X线中的一个或另一个。 互连在相邻X线对之间的半导体器件单元响应于施加在多条Y线上的数字输入信号，以在该对相邻X线上产生不同的逻辑信号。

公开(公告)号：CA929235A

公开(公告)日：1973-06-26

申请号：CA109046

申请日：1971-03-30

Applicant: IBM

Inventor： JEN T ,  HO I ,  HOWELL P

IPC: G11C19/18 ,  G11C19/28

Abstract: 1345604 Semi-conductor data storage cell INTERNATIONAL BUSINESS MACHINES CORP 27 May 1971 [30 June 1970] 17441/71 Heading H3T [Also in Division G4] A capacitor storage cell C28, C33, T44, T46 has its stored data refreshed or maintained by a transistor 50 cross-coupled with T46 (Fig. 1). C28 is charged by a pulse 16 (Fig. 1A) at terminal 14 via R22, D24 and line 26, and discharged or not by T44 if the data input 10 is high or low respectively, when a negative pulse 56 occurs at T44 emitter 30; then C33 is charged by pulse 32 at 30 via R36, D38 and discharged or not by T46 when a negative pulse 52 occurs at T46 emitter 14 depending upon the stored voltage on C28. To regenerate the information stored to allow for leakage, a similar cycle of pulses is applied at times t 5 -t 8 but instead of T44 discharging C28 in dependence on the input, T50 is biased by a pulse 50 at 58 to discharge C28 or not according to the already stored level on C33. The transistor 50 may be replaced by a cross-coupled pair (T128, 130, Fig. 2, not shown) and in this case stored, information is maintained merely by a constantly applied negative level - V at their commoned emitters (134). A shift register (Fig. 3, not shown) has a plurality of these cells (156-m) in each row (150-n).

公开(公告)号：CA927929A

公开(公告)日：1973-06-05

申请号：CA106341

申请日：1971-02-26

Applicant: IBM

Inventor： HO I

IPC: G11C19/18

Abstract: A monolithic memory including a plurality of interconnected cells. Each cell includes a diode in series with bipolar device or transistor which is dynamically or pulse powered. Parasitic capacitors are used as storage elements.