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公开(公告)号：US3781793A
公开(公告)日：1973-12-25
申请号：US3781793D
申请日：1972-04-10
Applicant: IBM
CPC classification number: G06F11/10
Abstract: An error detection system of n inputs is adaptable for fabrication in large scale integrated circuit form. An integrated circuit logic array provides a parity check in response to digital signals received via X and Y decoders. Reduction in the number of array cells and the X and Y driving decoder circuits is obtained by interconnecting even parity subgroups and odd parity subgroups of lines from the X and Y decoders to provide even master parity lines and odd master parity lines. A logic array having less than 2n operative cells compares the signals on the master lines and generates an error parity signal.
Abstract translation: n个输入的误差检测系统适用于大规模集成电路形式的制造。 集成电路逻辑阵列响应于经由X和Y解码器接收的数字信号提供奇偶校验。 通过将来自X和Y解码器的偶校验子组和奇校验子组相互连接来提供阵列单元数量和X和Y驱动解码器电路的减少，以提供偶校验奇偶校验线和奇数主奇偶校验线。 具有小于2n个操作单元的逻辑阵列比较主线上的信号并产生误差奇偶校验信号。
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公开(公告)号：US3798606A
公开(公告)日：1974-03-19
申请号：US3798606D
申请日：1971-12-17
Applicant: IBM
IPC: G06F12/16 , G06F1/00 , G06F7/00 , G06F11/10 , G06F11/18 , G06F15/78 , H03H9/02 , G06F11/00 , G06F13/00
CPC classification number: G06F11/184 , G06F1/00 , G06F7/00 , G06F11/10
Abstract: A monolithic circuit bit partitioned computer system for processing M bits of data comprising a substrate for providing electrical interconnection paths to a plurality of M monolithic circuit modules. Each of the M modules includes distinct decoder means, memory means, elemental quasi-arithmetic means and control circuitry, and each of the M modules are uniquely associated with the distinct ones of the M bits of data for collectively and universally processing the M bits of data.
Abstract translation: 一种用于处理M位数据的单片电路位分割计算机系统，包括用于提供到多个M个单片电路模块的电互连路径的衬底。 每个M个模块包括不同的解码器装置，存储装置，元素准运算装置和控制电路，并且M个模块中的每一个与M个数据位中的不同的一个数据唯一地相关联，用于共同和普遍地处理M位 数据。
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Patent Agency Ranking
公开(公告)号：US3735105A
公开(公告)日：1973-05-22
申请号：US3735105D
申请日：1971-06-11
Applicant: IBM
Inventor： MALEY G
CPC classification number: G06F11/1008 , G06F11/073 , G06F11/0772 , G06F11/10 , G06F11/1076 , G11C11/00 , G11C29/48
Abstract: A memory correcting system in accordance with this disclosure is an integral part of a digital electronic computer having a monolithic memory. The memory correcting system detects, records and analyzes errors occurring during normal operation of the computer. Also, the memory correcting system systematically addresses the monolithic memory on a cycle stealing basis monitoring the general health of the monolithic memory. The systematic reading and writing of all monolithic memory locations prevents the accumulating effects of random errors. By detecting single errors as rapidly as possible, the probability of acquiring additional errors that are above the correcting capabilities of the redundancy code are avoided.
Abstract translation: 根据本公开的存储器校正系统是具有单片存储器的数字电子计算机的组成部分。 存储器校正系统检测，记录和分析在计算机的正常操作期间发生的错误。 此外，存储器校正系统以循环窃取为基础系统地处理单片存储器，监控单片存储器的总体健康状况。 所有单片存储器位置的系统读写可以防止随机错误的累积效应。 通过尽可能快地检测单个错误，避免了获得高于冗余码的校正能力的附加错误的概率。
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4.发明授权
公开(公告)号：US3843953A
公开(公告)日：1974-10-22
申请号：US41690973
申请日：1973-11-19
Applicant: IBM
CPC classification number: G06F9/5016 , G06F11/3419
Abstract: Disclosed is apparatus in a computer for selecting the usage of functionally severable parts of the computer, for example, the amount of memory used by a computer having a plurality of memory partitions and an operating program such as the IBM OS/360 supervisor program for determining the allocation and activation of memory space. In the example given the apparatus includes an added register having a plurality of latches linking the ALU output bus to control by enabling or disabling selectively one or more memory partitions in accordance with usage dictated by the operating system program since the register contents are changeable only when the system is in the supervisor state. A meter is coupled to the memories to indicate elapsed time of use of the memory partitions so as to permit charging of a customer based upon usage. The purpose of this abstract is to enable the public and the Patent Office to determine rapidly the subject matter of the technical disclosure of the application. This abstract is neither intended to define the invention of the application nor is it intended to be limiting as to the scope thereof.
Abstract translation: 公开了一种计算机中用于选择计算机的功能可分割部分的使用的装置，例如由具有多个存储器分区的计算机使用的存储器的量以及诸如IBM OS / 360管理程序之类的操作程序，用于确定 内存空间的分配和激活。 在该示例中，该装置包括具有多个锁存器的附加寄存器，该多个锁存器通过根据操作系统程序所使用的使用选择性地启用或禁用一个或多个存储器分区来将ALU输出总线链接到控制，因为寄存器内容仅在 该系统处于主管状态。 仪表与存储器耦合以指示使用存储器分区的经过时间，以便允许基于使用情况对客户进行充电。
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公开(公告)号：US3820086A
公开(公告)日：1974-06-25
申请号：US24907672
申请日：1972-05-01
Applicant: IBM
CPC classification number: G11C7/20 , G11C11/4116 , G11C17/08 , G11C17/12 , H03K3/286 , H03K3/356008 , H03K3/35606
Abstract: The disclosures describes a transistor storage cell operable both as a random access read/write memory cell or as a read only memory cell. The memory cell structure includes a bistable circuit adapted to be set into one of two stable conditions and an imbalancing means for providing structural asymmetry. The memory cell is operable either as a read/write cell or, by accessing the cell through the imbalancing means, the latent image provided by the structural asymmetry of the cell is read out without affecting the information contained in the cell from the read/write mode of operation.
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公开(公告)号：US3755793A
公开(公告)日：1973-08-28
申请号：US3755793D
申请日：1972-04-13
Applicant: IBM
IPC: G11C17/00 , G11C7/20 , G11C11/35 , G11C11/404 , G11C17/12 , H01L27/108 , G11C7/00 , G11C11/34 , H03K25/02
CPC classification number: G11C17/12 , G11C7/20 , G11C11/35 , G11C11/404 , H01L27/108
Abstract: A latent image memory is selectively operable as either a readwrite memory or a read-only memory. The memory comprises an array of cells each preferably consisting of a single active device. A first set of the cells are each adapted to store either one of two binary digits. A second set of the cells are each responsive to a first condition for storing either one of two binary digits and responsive to a second condition for storing only a single predetermined binary digit. Means are provided for selecting either the first condition to render the array operable as a read-write memory, or the second condition to render the array operable as a read-only memory. Each of the cells of the first set preferably comprises a field-effect transistor connected to a capacitor, and each of the cells of the second set preferably comprises a charge-coupled device.
Abstract translation: 潜像存储器可选择性地操作为读写存储器或只读存储器。 存储器包括每个优选由单个有源器件组成的单元阵列。 第一组单元适合于存储两个二进制数字之一。 第二组单元各自响应用于存储两个二进制数字中的一个的第一条件，并响应于仅存储单个预定二进制数字的第二条件。 提供了用于选择第一条件以使得阵列可操作为读写存储器的装置，或者用于使阵列可操作为只读存储器的第二条件。 第一组的每个单元优选地包括连接到电容器的场效应晶体管，并且第二组的每个单元优选地包括电荷耦合器件。
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