中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.021 seconds)

    Fuse for ic, and its manufacturing method (fuse structure with terminal parts existing in different heights which is electrically programmable, and its manufacturing method)
    11.
    发明专利
    Fuse for ic, and its manufacturing method (fuse structure with terminal parts existing in different heights which is electrically programmable, and its manufacturing method) 有权
    IC的保险丝及其制造方法（具有电气可编程的不同高端中的终端部件的保险丝结构及其制造方法）

    公开(公告)号：JP2007243176A

    公开(公告)日：2007-09-20

    申请号：JP2007039055

    申请日：2007-02-20

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： TONTI WILLIAM R ,  MANDELMAN JACK A ,  HSU LOUIS LU-CHEN ,  WILLIAM P HOVIS ,  YANG CHIH-CHAO

    IPC: H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide an electrically programmable fuse structure for IC, and its manufacturing method. SOLUTION: This electrically programmable fuse has a first terminal part and second terminal part that are interconnected with fuse and elements. The first terminal part and second terminal part exist in different heights to the support surface of the fuse structure. The interconnecting fuse element connects the height difference between the height of the first terminal part and the second terminal part. While the first terminal part and second terminal part are oriented to be parallel with the support surface, the fuse element include a part oriented to be a right angle to the support surface, and also include at least one right-angled curvature portion that connects at least one of the first terminal element and second terminal element and the part of the fuse element oriented to be right angle. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为IC提供电可编程熔丝结构及其制造方法。 解决方案：该电可编程熔丝具有与熔丝和元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分与熔丝结构的支撑表面存在不同的高度。 互连保险丝元件连接第一端子部分和第二端子部分的高度之间的高度差。 当第一端子部分和第二端子部分被取向为与支撑表面平行时，熔丝元件包括定向成与支撑表面成直角的部分，并且还包括至少一个直角曲率部分，其连接在 第一端子元件和第二端子元件中的至少一个和熔丝元件的一部分被定向为直角。 版权所有（C）2007，JPO＆INPIT

    FIELD-EFFECT TRANSISTOR AND MANUFACTURE THEREOF
    12.
    发明专利
    FIELD-EFFECT TRANSISTOR AND MANUFACTURE THEREOF 失效

    公开(公告)号：JPH11251579A

    公开(公告)日：1999-09-17

    申请号：JP507999

    申请日：1999-01-12

    Applicant: IBM

    Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

    IPC: H01L29/78 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/10 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To provide a field-effect transistor having a substantially isolated body. SOLUTION: This field-effect transistor as an insulated gate field-effect transistor 10 has a device region 17, formed on a semiconductor material-made substantially electrically isolated region contact a semiconductor substrate 16 via a neck region 13 capable of exchanging charged carriers with the semiconductor substrate 16. The device region 17 of the transistor 10 is isolated from the electric contact to the substrate 16 at a surface other than that of the neck region 13.

    Semiconductor circuit for leakage current mitigation and method of detecting and mitigating leakage current runaway
    14.
    发明专利
    Semiconductor circuit for leakage current mitigation and method of detecting and mitigating leakage current runaway 有权
    用于泄漏电流减小的半导体电路和漏电流电流检测和减轻的方法

    公开(公告)号：JP2011015396A

    公开(公告)日：2011-01-20

    申请号：JP2010142690

    申请日：2010-06-23

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JOSHI RAJIV VASANT ,  YANG ZHIJIAN ,  GUO JONG-RU ,  WANG PING-CHUAN ,  HSU LOUIS LU-CHEN

    IPC: H03K5/08 ,  H01L21/822 ,  H01L27/04 ,  H03F1/52

    CPC classification number: H03K17/0822

    Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and method for mitigating a leakage current of a semiconductor device before catastrophic leakage current runaway occurs.SOLUTION: A leakage current shift monitor unit 20 is electrically connected to an output node of a leakage current target unit 10 and collects leakage currents from a selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator 40 receives and compares the outputs of the current shift monitor unit 20 and a reference voltage generator 30. The comparator 40 propagates an alert signal to the leakage current target unit 10 when the leakage voltage output from the leakage current shift monitor unit 20 exceeds the reference voltage, that is, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal attains leak mitigation also including a repair voltage to be applied to a gate of the target semiconductor device.

    Abstract translation: 要解决的问题：提供一种在灾难性漏电流失控之前减轻半导体器件的漏电流的装置和方法。解决方案：泄漏电流移动监视器单元20电连接到漏电流目标单元10的输出节点 并从所选择的目标半导体器件收集泄漏电流两个连续的预定义时间周期，并测量所收集的漏电流之间的差异。 比较器40接收并比较当前移动监视器单元20和参考电压发生器30的输出。当从泄漏电流移动监视单元20输​​出的泄漏电压超过时，比较器40向泄漏电流目标单元10传播报警信号 参考电压，即表示泄漏电流即将接近灾难性失控水平的条件。 该警报信号还实现泄漏减轻，还包括要施加到目标半导体器件的栅极的修复​​电压。

    Interconnect structure with barrier-redundancy constituent, and method of forming interconnect structure
    15.
    发明专利
    Interconnect structure with barrier-redundancy constituent, and method of forming interconnect structure 有权
    具有障碍物冗余结构的互连结构以及形成互连结构的方法

    公开(公告)号：JP2007251155A

    公开(公告)日：2007-09-27

    申请号：JP2007039112

    申请日：2007-02-20

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： YANG CHIH-CHAO ,  HSU LOUIS LU-CHEN

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L21/76849 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnect structure having a barrier-redundancy constituent, and a method of forming the interconnect structure.
    SOLUTION: A via diffusion barrier 30 exists on a portion of a conductive line 20. A conductive material 54 existing on a portion having no barrier 30 on the conductive line 20 provides an electrical path between a conductive line diffusion barrier 22 and the via diffusion barrier 30. Accordingly, an internal barrier-redundancy constituent is formed, using the conductive material 54, the conductive line diffusion barrier 22 and the via diffusion barrier 30. This electrical path to be provided by the barrier-redundancy constituent can avoid a sudden circuit open resulted from EM failure of the via bottom. Thus, after the EM failure is detected by a monitoring device, the barrier-redundancy constituent for providing a sufficient time for chip replacement or system operation adjustment is provided to the interconnect structure.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有阻挡冗余部件的互连结构以及形成互连结构的方法。 解决方案：通孔扩散阻挡层30存在于导电线20的一部分上。存在于导电线20上的不具有阻挡层30的部分上的导电材料54提供导电线扩散阻挡层22和 因此，使用导电材料54，导电线扩散阻挡层22和通孔扩散阻挡层30形成内部阻挡 - 冗余部件。由阻挡冗余部件提供的电路可以避免 由于通孔底部的EM故障导致突然断路。 因此，在通过监视装置检测到EM故障之后，向互连结构提供用于为芯片更换或系统操作调整提供足够时间的屏障冗余部件。 版权所有（C）2007，JPO＆INPIT

    ACTIVE FET BODY DEVICE AND MANUFACTURE THEREFOR
    17.
    发明专利
    ACTIVE FET BODY DEVICE AND MANUFACTURE THEREFOR 失效

    公开(公告)号：JP2000058861A

    公开(公告)日：2000-02-25

    申请号：JP22482799

    申请日：1999-08-09

    Applicant: IBM

    Inventor： ASSADERAGHI FARIBORZ ,  BERTIN CLAUDE L ,  GAMBINO JEFFREY P ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

    IPC: H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/84 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To obtain an active FET body device capable of balancing high-speed electric charges, decreasing off-current, and increasing on-current. SOLUTION: This embodiment comprises a silicon substrate 2, a silicon dioxide layer 3, a monocrystal silicon layer 4, a silicon dioxide layer 5, a spacer 13 of N+ doped polysilicon, a conformal layer 15 of a conductive diffusion preventing substance, a metal silicide layer 16, a CVD silicon dioxide layer 17, an insulator spacer 18, a silicon oxide layer 19, and a polysilicon 21. In an off-state, a gate contact with a body holds the body at a low word line level. In this state, a threshold takes a larger value. In addition to a voltage added to the N+ part 13 of a gate conductor, a potential from the body to a source rises. As a result, if the device is turned on, Vt lowers. By the effects of a dynamic Vt fall accompanied by a low off-current, this embodiment is suitable for a device using a very low voltage.

    VERY SMALL DRAM CELL AND FORMING METHOD THEREOF
    18.
    发明专利
    VERY SMALL DRAM CELL AND FORMING METHOD THEREOF 失效

    公开(公告)号：JP2000022100A

    公开(公告)日：2000-01-21

    申请号：JP13219499

    申请日：1999-05-13

    Applicant: IBM ,  SIEMENS AG

    Inventor： HOENIGSCHMID HEINZ ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

    IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a structure related to a semiconductor memory cell whose size is less than 4.5F2 in a case where F denotes the minimum dimension of a lithography techinique, and a manufacturing method thereof. SOLUTION: A semiconductor memory cell comprises a memory capacitor 12 formed in a trench, a transfer device formed in a mesa region which extends on the substantial arc of the periphery of the trench and is electrically isolated, and a buried strap which electrically connects the transfer device to the memory capacitors, wherein the transfer device comprises a controlled conduction channel located at a prescribed position on the arc removed from the buried strap.

    19.
    发明专利
    未知

    公开(公告)号：DE69307274D1

    公开(公告)日：1997-02-20

    申请号：DE69307274

    申请日：1993-10-05

    Applicant: IBM

    Inventor： BUTI TAQI N ,  JOSHI RAJIV V ,  SHEPARD JOSEPH F ,  HSU LOUIS LU-CHEN

    IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L23/535

    Abstract: A wafer structure (10) suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate (20) having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads (24) of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads (22) of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps (28) of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate (30) having an oxide layer (32) thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

Patent Agency Ranking