中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

47 records (took 0.024 seconds)

    EQUIPMENT TO CORRECT ABERRATIONS OF A CATHODE-RAY BEAM
    11.
    发明专利
    EQUIPMENT TO CORRECT ABERRATIONS OF A CATHODE-RAY BEAM 未知

    公开(公告)号：DE3065630D1

    公开(公告)日：1983-12-22

    申请号：DE3065630

    申请日：1980-10-23

    Applicant: IBM

    Inventor： JUDD IAN DAVID

    IPC: H04N3/23 ,  H04N3/26 ,  H04N9/28 ,  H04N17/04 ,  H04N3/22

    Abstract: Aberrations of an electron beam are corrected as the beam is scanned across the screen of a cathode ray tube by deriving correction signals from stored digital values by means of the calculus of finite differences. The digital values, which are the initial differences of polynomial correction functions, are held in store 10 and summed in adder 20, the results being converted by digital-to-analog converter 50 to analog signals and supplied to the cathode ray tube. Provision is made for the reduction of error in the calculations by shifting higher order differences relative to lower order differences before addition. The circuitry may be implemented on a single chip. Preferably, the invention is applied to the correction of misconvergence in a shadow mask tube.

    12.
    发明专利
    未知

    公开(公告)号：DE2754230A1

    公开(公告)日：1978-06-22

    申请号：DE2754230

    申请日：1977-12-06

    Applicant: IBM

    Inventor： JUDD IAN DAVID ,  MINSHULL JOHN FRANCIS

    IPC: G06F3/12 ,  G06K9/54 ,  G06T3/00 ,  G06T9/20 ,  G09G5/24 ,  G06K9/00

    Abstract: 1517869 Image encoding apparatus INTERNATIONAL BUSINESS MACHINES CORP 20 Dec 1976 53034/76 Heading H4P Data in the form of a stream of bits representing picture elements (pels), derived from the raster scanning of a document 1, is stored in compressed form in a store 8 which can be accessed so that the data pertaining to the stored document can be transmitted to a receiver 13 or can be expanded in a decompressor 9 for plotting or printing by a plotter 10 or for display on a display unit. The required compression is effected by passing the original bit stream through a pel stripper 3 where bits are removed to leave a processed bit pattern in which the bits represent predominantly single-pel-width strokes constituting either the outlines or the centre lines of characters. A segment follower 6 detects contiguous bits and produces a series of segments representing the tracked strokes. Each segment is coded in an encoder 7 into code words representing the shape of the segments and code words representing the end points of the segments, the segment bit thus produced being stored in the store 8. The stripping process is described with reference to Fig. 2 (not shown), whilst the constraints which determine whether a pel is or is not stripped from the original bit stream are described with reference to Figs. 5 and 6 (not shown). Suitable arrangements for the units 3, 6 and 7 are described with reference to Figs. 7 to 13 (not shown).

    Writing further new data in a raid array that stores data and parity in a different block size
    14.
    发明专利
    Writing further new data in a raid array that stores data and parity in a different block size 未知

    公开(公告)号：GB2493586A

    公开(公告)日：2013-02-13

    申请号：GB201208691

    申请日：2012-05-17

    Applicant: IBM

    Inventor： BENHASE MICHAEL THOMAS ,  NIELSEN KARL ALLEN ,  JUDD IAN DAVID ,  MOERTL DANIEL

    IPC: G06F11/10

    Abstract: A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and. the new parity aligned to the blocks of the second block size, wherein 'portions of the old data that are not overwritten by the RATD controller are also written to the blocks of the second block size. This allows efficient writing and storage of 512 byte blocks in newer disks with 4 Kilobyte block memory spaces.

    SYSTEM INPUT/OUTPUT INTERFACE DESIGN FOR SCALING.
    15.
    发明专利
    SYSTEM INPUT/OUTPUT INTERFACE DESIGN FOR SCALING. 未知

    公开(公告)号：MY122111A

    公开(公告)日：2006-03-31

    申请号：MYPI9803080

    申请日：1998-07-07

    Applicant: IBM

    Inventor： BEUKEMA BRUCE LEROY ,  BUCKLAND PATRICK ALLEN ,  CHEN WEN-TZER THOMAS ,  ELKO DAVID ARLEN ,  JUDD IAN DAVID ,  RECIO RENATO JOHN

    IPC: G06F13/28 ,  G06F3/00 ,  G06F9/06 ,  G06F12/08

    Abstract: THE SYSTEM I/O INTERFACE (24) AND ITS DATA STRUCTURE (26) ARE DESIGNED TO MINIMIZE THE HOST CPU UTILIZATION IN DRIVING AN ADAPTER (18, 20). THE INTERFACE IS ALSO DESIGNED TO REDUCE THE SYSTEM INTERFERENCE IN PROCESSING I/O REQUESTS. TO ELIMINATE THE NEED OF USING PIO INSTRUCTIONS, THE COMMAND/STATUS BLOCKS FOR EXCHANGING MESSAGES BETWEEN THE SYSTEM (10) AND THE ADAPTER RESIDE IN THE SYSTEM MEMORY (14). THE DATA STRUCTURE IS DESIGNED TO AVOID "SHARE WRITE" ENTRIES IN ORDER TO FURTHER MINIMIZE THE OVERHEAD OF MAINTAINING EACH COHERENCY WHEN UPDATING AN ENTRY IN THE CACHE EITHER CONCURRENTLY OR SEQUENTIALLY BY BOTH ADAPTER AND SYSTEM CPU (12). FURTHER, THE DATA STRUCTURE OF THE CONTROL AND STATUS BLOCKS IS RESIDED IN THE SYSTEM MEMORY. THE SYSTEM CPU USES STORE INSTRUCTION TO PREPARE CONTROL BLOCKS AND LOAD INSTRUCTION TO READ FROM COMPLETION STATUS BLOCKS; WHILE THE ADAPTER WILL RELY ON ITS DMA ENGINE TO MOVE DATA TO/FROM SYSTEM MEMORY IN ACCESSING CONTROL/STATUS BLOCKS.(FIG. 1)

    VIDEO DISPLAY SYSTEM
    17.
    发明专利
    VIDEO DISPLAY SYSTEM 未知

    公开(公告)号：DE3270136D1

    公开(公告)日：1986-04-30

    申请号：DE3270136

    申请日：1982-09-29

    Applicant: IBM

    Inventor： JUDD IAN DAVID ,  FARR ROBERT WILLIAM ERIC

    IPC: G09G5/36 ,  G09G1/00 ,  G09G3/20 ,  G09G5/00 ,  G09G5/24 ,  G09G5/32 ,  G09G1/16

    Abstract: In order to compensate for image distortion introduced into a digitally-controlled raster-scan CRT by the finite video amplifier rise and fall times, the digital video drive waveform is subject to selective pulse stretching to extend where possible the duration of pels which represent critical features of the image. This is achieved by decoding means for examining each pel at least in relation to its two immediate neighbors on either side in order to detect predetermined relationships between the values of the pels, and retiming means for selectively advancing or delaying the transitions between consecutive pels of different value in accordance with the relationships so detected. In one embodiment, suitable for multibit or single bit video, the decoding means comprises means (40, 25) for comparing each pel with its immediate successor, a shift register (26 to 28) for storing the result of each comparison together with the results of a plurality of immediately preceding comparisons, and a logic circuit (30 to 33) connected to the shift register stages, and the retiming means comprises a delay path (41 to 44) for the waveform having an output register (44) and means (34 to 39) responsive to the logic circuit for clocking the output register at a predetermined time in relation to non-selected transitions, earlier than the said predetermined time in relation to transitions selected for advancement, and later than the said predetermined time in relation to transitions selected for delay.

    Selective restoration of data from non-volatile storage to volatile memory
    19.
    发明专利
    Selective restoration of data from non-volatile storage to volatile memory 未知

    公开(公告)号：GB2510180A

    公开(公告)日：2014-07-30

    申请号：GB201301504

    申请日：2013-01-29

    Applicant: IBM

    Inventor： JUDD IAN DAVID

    IPC: G06F1/30 ,  G06F11/14

    Abstract: A method of controlling data transfers between a volatile memory means and a non-volatile storage means, the volatile memory means being on a memory device operatively coupled to a computer system, the data transfers comprising: storing data from the volatile memory means to the non-volatile storage means when a power source of the computer system fails, where the method comprises, following re-establishment of the previously failed power source, selectively restoring persistent data from the non-volatile storage means to the volatile memory means by a controller software after power-on self-test (POST) restart operations. The storing of data is carried out by a hardware control module and the selective restoring of data is initiated by a storage controller computer program that is configured to be loaded into the computer memory system and executed following re-establishment of the primary power source. The computer program requests allocation of memory space in the volatile memory means for restoring persistent data. The memory device may comprise an external interface implemented by a multiplexer, being a port selector providing a serial advanced technology attachment (SATA) external interface, and the memory device may be a non-volatile dual in line memory module (NV-DIMM). Volatile memory may be dynamic random access memory (DRAM) and non-volatile memory may be flash or a solid state storage drive.

Patent Agency Ranking