公开(公告)号：JPH10289154A

公开(公告)日：1998-10-27

申请号：JP7869098

申请日：1998-03-26

Applicant: IBM

Inventor： RAVI KUMER ARIMIRI ,  JOHN STEPHEN DODDSON ,  KAISER JOHN MICHAEL ,  JERRY DON LEWIS

IPC: G06F15/16 ,  G06F12/08 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To improve the memory waiting time caused by a reading type operation by making a requester processor issue a message to try to read an unchanged copy of the value that is exclusively held in a cache and them making the cache transfer an answer to show that it can supply the value. SOLUTION: The value is loaded from an address of a memory device to the 1st one of plural caches which are related to the processors of a computer system, and a mark is added to the cache to show that it includes an unchanged copy of the value held exclusively. Then a requester processor issues a message to show to try to read the value from an address of a memory device, and the 1st cache transfers an answer to show that it can supply the value. Under such conditions, a protocol including the R which designates a block that is latest referred to is used in addition to the changing, exclusive, shared and invalid states in order to confirm the cache that owns the unchanged value.

公开(公告)号：JP2770936B2

公开(公告)日：1998-07-02

申请号：JP24830291

申请日：1991-09-02

Applicant: IBM

Inventor： KAISER JOHN MICHAEL ,  YOUNGBLOOD LOYAL DAVID

IPC: G06F15/163 ,  G06F13/00 ,  G06F13/14 ,  G06F15/173 ,  H04L12/00 ,  H04L12/44

公开(公告)号：JPH04227152A

公开(公告)日：1992-08-17

申请号：JP25296191

申请日：1991-09-04

Applicant: IBM

Inventor： KAISER JOHN MICHAEL ,  ST CLAIR JOE CHRISTOPHER

IPC: G06F15/163 ,  G06F13/14 ,  G06F13/38 ,  H04Q3/52

Abstract: PURPOSE: To give a communication route between two devices among many devices by discriminating the occurrence of a change in communication channel and monitoring the communication between the devices for changing the communication channel in accordance with the occurrence of the change. CONSTITUTION: Each port (for example, 30) is connected to a port arbitration bus 50, a port control bus 52, and data transfer lines 54 and 55. Each port is also connected to a 16×16 matrix switch 40 through the data lines. The switch 40 forms cross point interconnection between ports. Each port performs photoelectric conversion so that information can be delivered electrically between ports. The port 30 first tries the connection to another port 32 and requests the permission of using the arbitration bus 50 through a bus arbitrator 38. When the port 30 receives the permission, a connection request is delivered to the port 32 through the control bus 32 and a status signal is received. The port 30 refuses a transfer request by returning the busy signal shown by the chained-line arrow 56 to the port 32.

公开(公告)号：AT231257T

公开(公告)日：2003-02-15

申请号：AT95480127

申请日：1995-09-08

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  KAISER JOHN MICHAEL

IPC: G06F15/16 ,  G06F13/362 ,  G06F13/364 ,  G06F15/177

Abstract: A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

公开(公告)号：CZ360499A3

公开(公告)日：2000-07-12

申请号：CZ360499

申请日：1998-04-03

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  KAISER JOHN MICHAEL ,  LEWIS JERRY DON

IPC: G06F12/0806 ,  G06F12/08

公开(公告)号：SG66439A1

公开(公告)日：1999-07-20

申请号：SG1998000511

申请日：1998-03-12

Applicant: IBM

Inventor： KAISER JOHN MICHAEL ,  MAULE WARREN EDWARD ,  MIRABELLA ROBERT DOMINICK ,  VICTOR DAVID WAYNE

IPC: G06F12/04 ,  G06F5/00 ,  G06F7/76 ,  G06F13/40 ,  G06F13/00

Abstract: To present a consistent image of storage facilities to components in Bi-modal Endian PowerPC system enviromnents, provision is made for transferring data between system components in the appropriate Endian format. Endian conversion function can be incorporated into the memory controller subsystem by adding byte-lane swapping logic on the inbound and outbound I/O data paths. With this structure, inbound data from the processor and memory bus will be converted to true Little Endian order before being sent to I/O devices. Likewise, true Little Endian data from I/O devices targeted for the processor or memory is modified to reflect the PowerPC Little Endian byte ordering convention.

公开(公告)号：HU215629B

公开(公告)日：1999-01-28

申请号：HU398591

申请日：1991-12-17

Applicant: IBM

Inventor： KAISER JOHN MICHAEL ,  YOUNGBLOOD LOYAL DAVID

IPC: G06F13/00 ,  G06F15/163 ,  G06F13/14 ,  G06F15/173 ,  H04L12/00

Abstract: A communications network including several ports 30, 32, 34, 36, 42, 44, 46 and 48 where each port is connected to at least one data processing system element. The ports are interconnected by an information bus 52. Additionally, the ports are connected to a matrix switch 40 that has the capability of providing a direct communications channel between any two of the ports. Each port includes control circuitry for communicating with other ports over the bus 52 and, through the bus, regulating the matrix switch in order for the matrix switch 40 to provide the direct communication channels between two ports.

公开(公告)号：DE69128133T2

公开(公告)日：1998-05-20

申请号：DE69128133

申请日：1991-12-18

Applicant: IBM

Inventor： KAISER JOHN MICHAEL ,  YOUNGBLOOD LOYAL DAVID

IPC: G06F15/163 ,  G06F13/00 ,  G06F13/14 ,  G06F15/173 ,  H04L12/00 ,  G06F15/16

Abstract: A communications network including several ports 30, 32, 34, 36, 42, 44, 46 and 48 where each port is connected to at least one data processing system element. The ports are interconnected by an information bus 52. Additionally, the ports are connected to a matrix switch 40 that has the capability of providing a direct communications channel between any two of the ports. Each port includes control circuitry for communicating with other ports over the bus 52 and, through the bus, regulating the matrix switch in order for the matrix switch 40 to provide the direct communication channels between two ports.

公开(公告)号：CZ385291A3

公开(公告)日：1995-03-15

申请号：CS385291

申请日：1991-12-17

Applicant: IBM

Inventor： KAISER JOHN MICHAEL ,  YOUNGBLOOD LOYAL DAVID

IPC: G06F15/163 ,  G06F13/00 ,  G06F13/14 ,  G06F15/173 ,  H04L12/00

Abstract: A communications network including several ports 30, 32, 34, 36, 42, 44, 46 and 48 where each port is connected to at least one data processing system element. The ports are interconnected by an information bus 52. Additionally, the ports are connected to a matrix switch 40 that has the capability of providing a direct communications channel between any two of the ports. Each port includes control circuitry for communicating with other ports over the bus 52 and, through the bus, regulating the matrix switch in order for the matrix switch 40 to provide the direct communication channels between two ports.

公开(公告)号：PL292847A1

公开(公告)日：1992-09-07

申请号：PL29284791

申请日：1991-12-18

Applicant: IBM

Inventor： KAISER JOHN MICHAEL ,  CLAIR JOE CHRISTOPHER ST

IPC: G06F15/163 ,  G06F13/14 ,  G06F13/38 ,  H04Q3/52 ,  G06F15/16

Abstract: A communication system for providing a communication path between two of a plurality of devices. A first port 30 is connected to one device and a second port 32 is connected to a second device. A switch 40 connects the two ports for communications connection between the ports in response to commands from the devices to each other. The switch includes the capability of monitoring communications between the devices and determining when a change is to be made in the communications path and then making the change accordingly.