公开(公告)号：DE3581910D1

公开(公告)日：1991-04-04

申请号：DE3581910

申请日：1985-10-17

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: G11C11/401 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4074

Abstract: A memory array is provided which includes a common sense line (SL) to which is connected first and second series of cells, each cell of each series includes a storage capacitor (C), switching means (T) and a bit line (BL) connected to a plate of the storage capacitor (C), with a common word line (WL) connected to the control electrodes of each of the switching means. The switching means, preferably field effect transistors, of each series of cells have progressively higher threshold voltages beginning at the sense line, and the voltage applied to the common word line has a magnitude greater than that of the highest threshold voltage. Data is stored into or read from the storage capacitors by selecting the common word line and the bit line of the desired cell in a sequential manner.

公开(公告)号：AU580450B2

公开(公告)日：1989-01-12

申请号：AU6307286

申请日：1986-09-23

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  G11C11/24

Abstract: A memory cell (10) formed in a groove or trench (18) in a semiconductor substrate (26) is provided which includes a storage capacitor (30) located at the bottom and along the lower portion of the sidewalls of the trench, a bit/sense line (32) disposed at the surface of the semiconductor substrate adjacent to the trench, a transfer device (34) or transistor located on the sidewall of the trench between the capacitor and the bit/sense line and a field (36) for electrically isolating the storage capacitor from an adjacent cell formed in the same semiconductor substrate.

公开(公告)号：BR8306653A

公开(公告)日：1984-07-31

申请号：BR8306653

申请日：1983-12-02

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  GEIPEL HENRY JOHN JR ,  KENNEY DONALD MCALPINE

IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/04 ,  H01L29/66

Abstract: A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

公开(公告)号：DE2316520A1

公开(公告)日：1973-10-11

申请号：DE2316520

申请日：1973-04-03

Applicant: IBM

Inventor： FITZGIBBONS WILLIAM ALOYSIUS ,  KENNEY DONALD MCALPINE ,  MICHAUD DONALD ADRIAN

IPC: C30B31/02 ,  H01L21/22 ,  H01L21/225 ,  H01L21/306 ,  B01J17/34

Abstract: 1397684 Diffusion in semi-conductors INTERNATIONAL BUSINESS MACHINES CORP 8 March 1973 [6 April 1972] 11389/73 Heading H1K In a semi-conductor diffusion process an oxide layer containing the dopant is first vapour deposited on the semi-conductor body under conditions such that a dopant-rich interface layer of a material containing both the semiconductor and the dopant forms beneath the oxide layer and an initial concentration of the dopant enters a shallow layer of the semiconductor beneath the interface layer. The atmosphere around the body is then altered to an oxidizing state, the other conditions preferably remaining unchanged, so that the interface layer is converted to a soluble oxide which is subsequently removed by etching together with the dopant-containing oxide layer thereon. A drive-in diffusion is then carried out, preferably in an oxidizing atmosphere, to redistribute the initial dopant concentration from the shallow layer. For a Si body with B as the dopant the dopant-containing oxide is B 2 O 3 deposited, in an aperture in an oxide mask, from a vapour whose source is boron nitride slices having their outer surfaces oxidized to form B 2 O 3 . An inert carrier gas such as nitrogen is used. The Si body is maintained at 800-1300‹ C. during the oxide deposition process. The interface layer formed in these conditions is believed to be SiB 6 , which converts to a soluble borosilicate glass on the addition of oxygen and/or steam to the atmosphere. As, as a dopant, and Ge, as a semiconductor material, are also mentioned.

公开(公告)号：DE69431867T2

公开(公告)日：2003-10-02

申请号：DE69431867

申请日：1994-10-07

Applicant: IBM

Inventor： BRONNER GARY BELA ,  KENNEY DONALD MCALPINE ,  DEBROSSE JOHN KENNETH

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

公开(公告)号：DE3855255T2

公开(公告)日：1996-11-21

申请号：DE3855255

申请日：1988-12-05

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/08 ,  H01L27/092 ,  H01L27/11 ,  H01L23/52 ,  H01L21/74 ,  H01L21/82

公开(公告)号：DE3855255D1

公开(公告)日：1996-06-05

申请号：DE3855255

申请日：1988-12-05

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/08 ,  H01L27/092 ,  H01L27/11 ,  H01L23/52 ,  H01L21/74 ,  H01L21/82

公开(公告)号：DE3689467T2

公开(公告)日：1994-06-23

申请号：DE3689467

申请日：1986-10-07

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A memory cell (10) formed in a groove or trench (18) in a semiconductor substrate (26) is provided which includes a storage capacitor (30) located at the bottom and along the lower portion of the sidewalls of the trench, a bit/sense line (32) disposed at the surface of the semiconductor substrate adjacent to the trench, a transfer device (34) or transistor located on the sidewall of the trench between the capacitor and the bit/sense line and a field (36) for electrically isolating the storage capacitor from an adjacent cell formed in the same semiconductor substrate.

公开(公告)号：DE3689467D1

公开(公告)日：1994-02-10

申请号：DE3689467

申请日：1986-10-07

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: A memory cell (10) formed in a groove or trench (18) in a semiconductor substrate (26) is provided which includes a storage capacitor (30) located at the bottom and along the lower portion of the sidewalls of the trench, a bit/sense line (32) disposed at the surface of the semiconductor substrate adjacent to the trench, a transfer device (34) or transistor located on the sidewall of the trench between the capacitor and the bit/sense line and a field (36) for electrically isolating the storage capacitor from an adjacent cell formed in the same semiconductor substrate.

公开(公告)号：AU6307286A

公开(公告)日：1987-05-07

申请号：AU6307286

申请日：1986-09-23

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  G11C11/24

Abstract: A memory cell (10) formed in a groove or trench (18) in a semiconductor substrate (26) is provided which includes a storage capacitor (30) located at the bottom and along the lower portion of the sidewalls of the trench, a bit/sense line (32) disposed at the surface of the semiconductor substrate adjacent to the trench, a transfer device (34) or transistor located on the sidewall of the trench between the capacitor and the bit/sense line and a field (36) for electrically isolating the storage capacitor from an adjacent cell formed in the same semiconductor substrate.