公开(公告)号：AT20507T

公开(公告)日：1986-07-15

申请号：AT80104358

申请日：1980-07-24

Applicant: IBM

Inventor： FORTINO ANDREAS GUILLERMO ,  GEIPEL HENRY JOHN JR ,  HELLER LAWRENCE GRIFFITH ,  SILVERMAN RONALD

IPC: H01L21/822 ,  G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/225 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112 ,  H01L29/08 ,  H01L29/78

公开(公告)号：AT26897T

公开(公告)日：1987-05-15

申请号：AT83110131

申请日：1983-10-11

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  GEIPEL HENRY JOHN JR ,  KENNEY DONALD MCALPINE

IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

Abstract: A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

公开(公告)号：IT1150032B

公开(公告)日：1986-12-10

申请号：IT2368880

申请日：1980-07-25

Applicant: IBM

Inventor： FORTINO ANDRES GUILLERMO ,  GEIPEL HENRY JOHN JR ,  HELLER LAWRENCE GRIFFITH ,  SILVERMAN RONALD

IPC: H01L21/822 ,  G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/225 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112 ,  H01L29/08 ,  H01L29/78 ,  H01C

Abstract: A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.

公开(公告)号：BR8306653A

公开(公告)日：1984-07-31

申请号：BR8306653

申请日：1983-12-02

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  GEIPEL HENRY JOHN JR ,  KENNEY DONALD MCALPINE

IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/04 ,  H01L29/66

Abstract: A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

公开(公告)号：DE3481148D1

公开(公告)日：1990-03-01

申请号：DE3481148

申请日：1984-11-30

Applicant: IBM

Inventor： GEIPEL HENRY JOHN JR ,  SCHAEFER CHARLES ANDREW ,  WHITE FRANCIS ROGER ,  WURSTHORN JOHN MICHAEL

IPC: H01L21/22 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/321 ,  H01L21/324 ,  H01L21/322

Abstract: A process is provided for fabricating a semiconductor structure wherein the structure has to be exposed to certain oxidizing conditions during certain of its processing steps, such as its high temperature annealing in an oxidizing ambient. It includes depositing a "sacrificial" layer, such as silicon, to provide a uniformly oxidizing surface during subsequent annealing operations. This sacrificial layer, which oxidizes uniformly, produces an oxide layer which also etches uniformly. Thus, after the annealing is completed, the surface oxide is removed through etching and the remaining sacrificial layer is then also removed through a different etching step.

公开(公告)号：DE3071648D1

公开(公告)日：1986-07-24

申请号：DE3071648

申请日：1980-07-24

Applicant: IBM

Inventor： FORTINO ANDREAS GUILLERMO ,  GEIPEL HENRY JOHN JR ,  HELLER LAWRENCE GRIFFITH ,  SILVERMAN RONALD

IPC: H01L21/822 ,  G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/225 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112 ,  H01L29/08 ,  H01L29/78

Abstract: A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.