公开(公告)号：JP2003008428A

公开(公告)日：2003-01-10

申请号：JP2002116448

申请日：2002-04-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： BRYANT ANDRES ,  COTTRELL PETER EDWIN ,  ELLIS-MONAGHAN JOHN JOSEPH ,  KETCHEN MARK B ,  NOWAK EDWARD J

IPC: H01L27/04 ,  G05F3/20 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K19/094

CPC classification number: G05F3/205 ,  H01L27/0218

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus for biasing ultra-low voltage logic circuits.
SOLUTION: An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and second power supply or ground. The gate and source of the first transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected to form an output connected to the bodies of the other transistors within the integrated circuit device.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于偏压超低电压逻辑电路的装置。 解决方案：集成电路器件包括多个晶体管和全局体偏置电路。 全局体偏置电路包括串联连接在电源和第二电源或地之间的第一晶体管和第二晶体管。 第一晶体管的栅极和源极连接到第二电源。 第一和第二晶体管的漏极和主体被连接以形成连接到集成电路器件内的其它晶体管的主体的输出端。

公开(公告)号：DE3378606D1

公开(公告)日：1989-01-05

申请号：DE3378606

申请日：1983-12-21

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  GARNACHE RICHARD RAYMOND ,  GEIPEL HENRY JOHN ,  TROUTMAN RONALD ROY

IPC: H01L29/78 ,  H01L21/31 ,  H01L21/76 ,  H01L23/29 ,  H01L23/552 ,  H01L23/54 ,  H01L23/28

公开(公告)号：DE3371264D1

公开(公告)日：1987-06-04

申请号：DE3371264

申请日：1983-10-11

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  GEIPEL HENRY JOHN ,  KENNEY DONALD MCALPINE

IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

Abstract: A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

公开(公告)号：AT26897T

公开(公告)日：1987-05-15

申请号：AT83110131

申请日：1983-10-11

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  GEIPEL HENRY JOHN JR ,  KENNEY DONALD MCALPINE

IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

Abstract: A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

公开(公告)号：DE3581852D1

公开(公告)日：1991-04-04

申请号：DE3581852

申请日：1985-06-24

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  CRAIG WILLIAM JAMES ,  TROUTMAN RONALD ROY

IPC: H01L27/08 ,  H01L21/761 ,  H01L27/02 ,  H01L27/092

Abstract: The overvoltage protection circuit, when used with CMOS circuits, protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region (16) of an opposite conductivity to that of the substrate (10, 12) defining a pocket region (18) having a conductivity type which is similar to that of the substrate (10, 12). A first PN junction diode (34) is formed in a portion of the well region (16) and a second PN junction diode (32) is formed in the pocket region (18). The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region (18) is connected to a Vss terminal which is normally grounded and the well region (16) is connected to a power supply VDD. The doping concentration in the well region (16) is predetermined to have a gradient so that minority carriers injected from one of the diodes in the well region will be repulsed and prevented from moving into the substrate region where they would be majority carriers and they could cause latch-up in the structure or at the very least adversely affect the voltage level of the substrate. Instead the injected carriers recombine in the well region (16) or are collected by the adjacent isolated pocket region (18). … When the second diode (32) is forward biased, the minority carriers are injected into the isolated pocket region (18) and are prevented from reaching the substrate (10) by the underlying well region (14). This prevents these carriers from affecting the operation of adjacent circuits.

公开(公告)号：DE3570016D1

公开(公告)日：1989-06-08

申请号：DE3570016

申请日：1985-07-09

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  CRAIG WILLIAM JAMES ,  TROUTMAN RONALD ROY

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

公开(公告)号：BR8306653A

公开(公告)日：1984-07-31

申请号：BR8306653

申请日：1983-12-02

Applicant: IBM

Inventor： COTTRELL PETER EDWIN ,  GEIPEL HENRY JOHN JR ,  KENNEY DONALD MCALPINE

IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/04 ,  H01L29/66

Abstract: A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.