公开(公告)号：JPH11149800A

公开(公告)日：1999-06-02

申请号：JP24707698

申请日：1998-09-01

Applicant: SIEMENS AG ,  IBM

Inventor： WONG HING ,  KIRIHATA TOSHIAKI ,  KRSNIK BOZIDAR

IPC: G06F1/06 ,  G01R31/28 ,  G01R31/30 ,  G06F1/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/12 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To perform arbitrary adjustment of internal timing easily and externally by deriving the timing of an internal control signal from an internal signal in case of normal operation mode and deriving it from an external signal being fed with an internal control signal from an external terminal in case of rest mode. SOLUTION: In case of normal access mode, a WL, timer 11 times up to generate an SA Enable signal and then an SA timer 12 times up to generate a Col nable signal. When a test mode signal (TM GSAE and TM CCSLE) is activated and the timers 11, 12 are disabled, a DRAM integrated circuit is switched to test mode. If a WL Enable signal is formed, it is formed not through the timer 11 but through an external signal '/G' and an NAND gate 13. Furthermore, the Col Enable signal is formed through an external signal '/CAS' and an NAND gate 16.

公开(公告)号：JPH06223572A

公开(公告)日：1994-08-12

申请号：JP24806793

申请日：1993-10-04

Applicant: IBM

Inventor： SAN HOO DONGU ,  KIRIHATA TOSHIAKI ,  HIYUN JIYON SHIN ,  SUNANAGA TOSHIO ,  TAIRA YOICHI ,  RUISU MADEISON TERUMAN

IPC: G11C11/409 ,  G11C11/407 ,  G11C11/4094

Abstract: PURPOSE: To reduce the power dissipating amounts of a bit line by providing a DRAM structure using a variable precharge voltage detecting technique. CONSTITUTION: In the end of a row address storage(RAS) cycle, a bit line 10 and a complementary bit 12 are short-circuited, and short-circuited through a line 32 with VEQ by equalizing devices 18, 20, and 22, and balancing is operated by bit line precharge in the next RAS cycle. This voltage is higher than the precharge voltage in the previous cycle. When a capacitance 88 of a memory cell to which access is performed stores 0V, the bit line precharge voltage is made lower than that in the previous RAS cycle. When a high level is stored in the cell capacitance of the cell connected with a word line and accessed in each following cycle, the same sequence is repeated in the following RAS cycle, and the bit line precharge voltage is increased in each cycle. Then, a bit line power can not be drawn from a DRAM power source by the balancing with a bit line pair voltage.

公开(公告)号：JPH0492287A

公开(公告)日：1992-03-25

申请号：JP20831690

申请日：1990-08-08

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  KIRIHATA TOSHIAKI ,  ROI EDOUIN SHIYUWARAIRE

IPC: G11C11/409 ,  G11C11/4091

Abstract: PURPOSE: To realize a DRAM capable of high speed operation by limiting a downward voltage swing of a low level side bit line to a prescribed voltage level higher than a reference voltage. CONSTITUTION: The downward voltage swing of the low level side bit line BLN generating by the activation of a first latch 10 is made to clamp to a prescribed bit line voltage level by controlling the voltage of a common node N1 of the first latch 10. And when FETs TN5, TN6 are continued to conduct, the voltage of the low level side bit line is dropped to about zero V. Hear, when the voltage of the low level side bit line BLN is dropped to a prescribed bit line low voltage level VBLL corresponding to a low level restore voltage by the activation of the latch 10, a PS1 and PS2 become low to turn off the TN5 and TN6. Therefore, the low level restore voltage is automatically provided to the low level side bit line.

公开(公告)号：JP2007234225A

公开(公告)日：2007-09-13

申请号：JP2007154901

申请日：2007-06-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KIRIHATA TOSHIAKI ,  DHONG SANG HOO ,  OH HWA-JOON ,  WORDEMAN MATTHEW

IPC: G11C11/401 ,  G11C11/41 ,  G06F12/08 ,  G11C7/10 ,  G11C11/409

CPC classification number: G06F12/0893 ,  G11C7/1006 ,  G11C2207/2245

Abstract: PROBLEM TO BE SOLVED: To improve access cycle time of a dynamic random access memory (DRAM) system having a plurality of memory cells constituted of rows and columns.
SOLUTION: A method comprises a step in which a destructive read mode is enabled, the destruction read mode is a mode for read out destructively a bit of information stored in a DRAM memory cell being addressed. A bit in which information is read destructively is stored temporarily in a temporary storage device. A delay write-back-mode is enabled, this delay write-back-mode is a mode for restoring bit of information in the DRAM memory cell being addressed afterward. Then, execution of the delay write-back-mode is scheduled in accordance with availability of space in the temporary storage device.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：改进具有由行和列构成的多个存储单元的动态随机存取存储器（DRAM）系统的访问周期时间。 解决方案：一种方法包括其中启用破坏性读取模式的步骤，破坏读取模式是用于破坏性地读出存储在正在寻址的DRAM存储器单元中的一位信息的模式。 信息被破坏性读取的位临时存储在临时存储装置中。 延迟回写模式被使能，该延迟写回模式是用于恢复之后寻址的DRAM存储单元中的信息位的模式。 然后，根据临时存储设备中的空间的可用性来调度延迟写回模式的执行。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2001006354A

公开(公告)日：2001-01-12

申请号：JP2000172863

申请日：2000-06-09

Applicant: IBM

Inventor： HANSON DAVID R ,  KIRIHATA TOSHIAKI

IPC: G11C11/413 ,  G11C7/06 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/419

Abstract: PROBLEM TO BE SOLVED: To enable operating a chip at a higher frequency by executing the overlap of operations by using a sense-amplifier circuit, two drivers connected to the circuit and a memory device having two lines of data buss lines connected to the circuit in order to receive data signals. SOLUTION: The operation of a circuit consisting of a sense amplifier 10, two NOR gates 11, 12 and global data busses MDQt, MDQc is controlled by 6 pieces of signals, that is, a writing gate signal WGTn, an MDQ reading and restoring signal DQRST, an MDQ equalizing signal MDQn, a sense amplifier equalizing signal GEQn, a sense amplifier switching signal SSASWn and a sense amplifier enabling signal SSAE, When the signal SSASWn is active, data on data busses MDQ are loaded to the sense amplifier 10 and when the signal SSAE is active, data on the data busses MDQ are amplified.

公开(公告)号：JPH11273394A

公开(公告)日：1999-10-08

申请号：JP2334499

申请日：1999-02-01

Applicant: Internatl Business Mach Corp ,  Siemens Ag ,  インターナショナル・ビジネス・マシーンズ・コーポレイション ,  シーメンス・アクチエンゲゼルシャフト

Inventor： KIRIHATA TOSHIAKI ,  PFEFFERL KARL-PETER

IPC: G11C29/04 ,  G11C29/00

CPC classification number: G11C29/808 ,  G11C29/812

Abstract: PROBLEM TO BE SOLVED: To obtain a method and a device for repairing a memory element by a selective domain redundancy substitution(SDRR) configuration after manufacturing and testing the memory element. SOLUTION: A memory array has a plurality of domains (210-0-210-15). A redundant array includes four redundant unit groups (220-0-220-3) (group A), 16 redundant unit groups (222-0-222-15) (group B) including each two redundant units, and 16 redundant unit groups (224-0-224-15) (group C) including each redundant unit. According to the trouble of each domain, the redundant unit group is selected, and a defective element is substituted for the redundant unit of the selected redundant unit group.

Abstract translation: 要解决的问题：在制造和测试存储元件之后，获得通过选择性域冗余替换（SDRR）配置来修复存储元件的方法和装置。 解决方案：存储器阵列具有多个域（210-0-210-15）。 冗余阵列包括四个冗余单元组（220-0-220-3）（组A），16个冗余单元组（222-0-222-15）（组B），包括每两个冗余单元，以及16个冗余单元组 （224-0-224-15）（C组），包括每个冗余单元。 根据每个域的故障，选择冗余单元组，并且将缺陷元件替换为所选冗余单元组的冗余单元。

公开(公告)号：JPH11273351A

公开(公告)日：1999-10-08

申请号：JP1813599

申请日：1999-01-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： HOSOKAWA KOHJI ,  KIRIHATA TOSHIAKI

IPC: G11C11/409 ,  G11C8/10 ,  G11C11/401

CPC classification number: G11C8/10

Abstract: PROBLEM TO BE SOLVED: To reduce the number of signal lines to transmit data with a less amount of current without precharging by providing a sense amplifier and an inverter connected for providing complimentary output and converting the complimentary signal to the single-ended data signal and then transmitting to one read/write drive line.
SOLUTION: A secondary sense amplifier unit 650 receives a data signal of memory array formed by MDQ architecture with a master bit line pair MDQ/MDQ bar and then sends to current mirror sense amplifiers (CMP) 600, 601. CMP 600, 601 generates the signal GD' via the corresponding signal GL and inverter 631. A driver consisting of a pair of NFET 620, PFET630 receives the signals GD, GD' and then sends the data to the input/output circuit by driving the single-ended bothway read/write drive lines RWD. The data on the drive line RWD is held by the latch 652 and this data swings only when it changes from the signal of the immediately preceding cycle.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：通过提供读取放大器和连接用于提供互补输出并将互补信号转换为单端数据信号的反相器，减少没有预充电的少量电流来传输数据的信号线的数量，然后 发送到一个读/写驱动线。 解决方案：次级读出放大器单元650接收具有主位线对MDQ / MDQ条的由MDQ架构形成的存储器阵列的数据信号，然后发送到电流镜像读出放大器（CMP）600,601。CMP 600,601产生 信号GD'通过对应的信号GL和反相器631.由一对NFET 620，PFET630组成的驱动器接收信号GD，GD'，然后通过驱动单端两路读/ 写驱动线RWD。 驱动线RWD上的数据由锁存器652保持，并且该数据仅在其从紧接在前的周期的信号变化时才摆动。

公开(公告)号：JPH1196790A

公开(公告)日：1999-04-09

申请号：JP19136298

申请日：1998-07-07

Applicant: IBM ,  SIEMENS AG

Inventor： KIRIHATA TOSHIAKI ,  GEEBURIERU DANIERU ,  JIYAN MAAKU DORUTEYU ,  KAARU PEETAA PUFUETSUFUERU

IPC: G11C29/44 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To enable realizing fault tolerant design being applicable to a memory of arbitrary size by enable using a efficient and effective replacement domain out of at least two variable domains in which one part is overlapped, and using redundant constitution as variable domain redundant replacement(VDRR). SOLUTION: In a variable domain A (m=16) constituted with VDRR and superimposed and other two domains, when an obstacle is common for two domains, an obstacle in other domain can be restored by using a redundant circuit in one domain. Thereby, the possible and best restoring domain cart be selected in accordance with a type and magnitude of an obstacle. A VDRR method can restore an obstacle distributed at random, while holding obstacle and hard obstacle can be restored with less redundant overhead.

公开(公告)号：JPH10275497A

公开(公告)日：1998-10-13

申请号：JP7683098

申请日：1998-03-25

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C29/04 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide fault tolerant design applicable to memory in any size by using redundant replacement configuration in variable size for selectively replacing a fault element with the redundant element in the same size. SOLUTION: The variable redundant array replacement configuration is provided with plural redundant units(RU) having variable number of redundant elements(RE) for each RU and at any RU, all the RE are simultaneously replaced by prescribed repair. For example, RU0-7 , RU8-11 , RU12-13 , RU14 and RU15 respectively have 1, 2, 4, 8 and 32 pieces of RE. At all the RU0-7 , single fault is repaired and at all the RU8-11 , the fault caused by short-circuiting generated between defective bit lines or elements is repaired. Then, the R12-13 , R14 and RU15 are secured for processing the much severe fault at a fault decoder or the like. Then, the RU is controlled by respectively correspondent redundant unit control circuit (RUCNT).

公开(公告)号：WO2014137548A3

公开(公告)日：2015-02-26

申请号：PCT/US2014015716

申请日：2014-02-11

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  PAONE PHIL ,  PATEL VIMAL ,  UHLMANN GREGORY J

IPC: H01L23/62 ,  H01L21/82

CPC classification number: H01H85/05 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first gate. The first source/drain area is coupled to the second end of the eFuse, the second source/drain area is coupled to ground, and the first gate is coupled to a first node. The eFuse cell includes a senseFET having a third source/drain area, a fourth source/drain area, and a second gate. The second gate is coupled to the first node, and the third source/drain area is coupled to a second node. The second node is coupled to an operation signal and the second end of the eFuse. The eFuse cell includes a select eFuse logic element having an input to receive a select eFuse signal and an output coupled to the first node.

Abstract translation: 实施例可以包括eFuse单元。 eFuse单元可以包括具有第一端和第二端的eFuse。 blowFET具有第一源极/漏极区域，第二源极/漏极区域和第一栅极。 第一源极/漏极区域耦合到eFuse的第二端，第二源极/漏极区域耦合到地，并且第一栅极耦合到第一节点。 eFuse单元包括具有第三源极/漏极区域，第四源极/漏极区域和第二栅极的感测FET。 第二栅极耦合到第一节点，并且第三源极/漏极区域耦合到第二节点。 第二节点耦合到操作信号和eFuse的第二端。 eFuse单元包括具有用于接收选择eFuse信号的输入和耦合到第一节点的输出的选择eFuse逻辑元件。