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公开(公告)号：DE3483301D1
公开(公告)日：1990-10-31
申请号：DE3483301
申请日：1984-07-05
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , RACKLEY DARWIN PRESTON , SAENZ JESUS ANDRES
Abstract: @ A raster scan display system includes a plurality of storage maps (MAPO to MAP4). These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide colour signals from which colour video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.
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公开(公告)号：AT50653T
公开(公告)日：1990-03-15
申请号：AT84107803
申请日：1984-07-05
Applicant: IBM
Inventor： KUMMER DAVID ALLEN
Abstract: A microcomputer includes a main memory system which is accessed, substantially independently, by the CPU and a subsystem, for example a video display subsystem (12,11). The memory system comprises a base memory (22) and an optional add-ori expansion memory (42). When only the base memory is installed, consecutive locations have consecutively numbered addresses, and both the CPU and subsystem access individual locations. When both memories are installed, one has even numbered addresses and the other odd numbered addresses. With both memories installed, the CPU still accesses individual locations, but the subsystem addresses even addresses to obtain, for each access, data from the even address and the next higher odd address, thereby accessing a location in both memories. Thus the memory bandwith for the subsystem is effectively doubled when the expansion memory is installed.
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公开(公告)号：DE3176950D1
公开(公告)日：1989-01-12
申请号：DE3176950
申请日：1981-08-12
Applicant: IBM
Inventor： EGGEBRECHT LEWIS CLARK , KUMMER DAVID ALLEN
IPC: G06F12/06
Abstract: A processor is provided with an address bus for manifesting a first set of address signals and a direct memory access control coupled to the address bus for manifesting a second lesser set of address signals. The processor accesses the storage by selectively operable channels. Programmable register are coupled to the address bus for manifesting a third set of address signals equal to, or less in number than the difference between the first and second setc. A decoder is responsive to the operation of the direct memory access control on behalf of a respective one of the operating channels for gating, to the address bus, the address signals manifested by the programmable register corresponding to the respective operating channel. This extends the addressing capability to enable direct storage access channels to operate simultaneously in the same or different storage page.
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公开(公告)号：MX157249A
公开(公告)日：1988-11-08
申请号：MX20231684
申请日：1984-08-09
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , SAENZ JESUS ANDRES , TRYNOSKY STEPHEN WAYNE
Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.
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公开(公告)号：DE3278982D1
公开(公告)日：1988-10-06
申请号：DE3278982
申请日：1982-06-29
Applicant: IBM
Inventor： DEAN MARK EDWARD , KUMMER DAVID ALLEN , SAENZ JESUS ANDRES
Abstract: A 3.58 MHz subcarrier signal and a 14.318 MHz clock signal are applied to three flipflops (50, 52 and 54) in such a manner that there appears on the output terminals (Q and Q) of the latches individual phase-shifted subcarriers having relative phases of 0°, 180°, 90°, 270°, 135° and 315°, respectively, representing the colors yellow, blue, red, cyan, magenta and green, respectively. Computer-generated digital color signals (+BLUE, +GREEN, +RED) are applied to the switching inputs (A, B, C) of a multiplexer (56) in order selectively to switch to the output of the multiplexer individual ones of the phase-shifted subcarriers in accordance with the code represented by the digital color signals. The individual subcarriers are combined in a summing circuit (62, 64) with television synchronizing and blanking pulses to produce a composite video color signal which is directly compatible with a conventional composite monitor and, after R.F. modulation, with a conventional television receiver. Brighter versions of the colors are obtained by increasing the direct current level (+INTENSITY) at the summing circuit.
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Patent Agency Ranking
公开(公告)号：GB2139007B
公开(公告)日：1986-10-01
申请号：GB8405863
申请日：1984-03-06
Applicant: IBM
Inventor： BREWER JAMES ARTHUR , KUMMER DAVID ALLEN , LANGGOOD JOHN KENNEDY
Abstract: A six-layer printed circuit card has first, third and sixth layers which are signal carrying layers for interconnecting various components forming a personal computer. The second and fifth layers are both ground plane layers and the fourth layer of the card is a voltage plane. The components on the printed circuit card include eight input/output (I/O) connectors J1 - J8 to which eight other cards controlling various I/O devices can be connected. Seven of the eight I/O connectors are interconnected to a conventional I/O bus. The eighth connector J8 is interconnected to some lines of the I/O bus and to some lines of the signal carrying layers which form an internal bus.
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公开(公告)号：DE3265998D1
公开(公告)日：1985-10-10
申请号：DE3265998
申请日：1982-05-12
Applicant: IBM
Inventor： EGGEBRECHT LEWIS CLARK , KUMMER DAVID ALLEN , SAENZ JESUS
Abstract: Two controller units (11, 12) controlling a single input/ output device such as a cathode ray tube (CRT) are synchronized by a command signal. Upon appearance of the command signal, the slave controller unit (12), which may have been running unsynchronized with the master controller (11), is stopped at the time for vertical retrace and remains stopped until vertical retrace time for the master controller. At this point, the slave controller is restarted in synchronism with the master controller and remains synchronized so long as both master and slave receive the same clock and the same screen refresh parameters.
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公开(公告)号：AU3098884A
公开(公告)日：1985-02-14
申请号：AU3098884
申请日：1984-07-24
Applicant: IBM
Inventor： KUMMER DAVID ALLEN
Abstract: A microcomputer includes a main memory system which is accessed, substantially independently, by the CPU and a subsystem, for example a video display subsystem (12,11). The memory system comprises a base memory (22) and an optional add-ori expansion memory (42). When only the base memory is installed, consecutive locations have consecutively numbered addresses, and both the CPU and subsystem access individual locations. When both memories are installed, one has even numbered addresses and the other odd numbered addresses. With both memories installed, the CPU still accesses individual locations, but the subsystem addresses even addresses to obtain, for each access, data from the even address and the next higher odd address, thereby accessing a location in both memories. Thus the memory bandwith for the subsystem is effectively doubled when the expansion memory is installed.
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公开(公告)号：GB2139007A
公开(公告)日：1984-10-31
申请号：GB8405863
申请日：1984-03-06
Applicant: IBM
Inventor： BREWER JAMES ARTHUR , KUMMER DAVID ALLEN , LANGGOOD JOHN KENNEDY
Abstract: A six-layer printed circuit card has first, third and sixth layers which are signal carrying layers for interconnecting various components forming a personal computer. The second and fifth layers are both ground plane layers and the fourth layer of the card is a voltage plane. The components on the printed circuit card include eight input/output (I/O) connectors J1 - J8 to which eight other cards controlling various I/O devices can be connected. Seven of the eight I/O connectors are interconnected to a conventional I/O bus. The eighth connector J8 is interconnected to some lines of the I/O bus and to some lines of the signal carrying layers which form an internal bus.
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公开(公告)号：FR2542556A3
公开(公告)日：1984-09-14
申请号：FR8321050
申请日：1983-12-28
Applicant: IBM
Inventor： BREWER JAMES ARTHUR , KUMMER DAVID ALLEN , LANGGOOD JOHN KENNEDY
Abstract: Printed-circuit board comprising six superposed layers, three of which are signal-flow layers, one is a layer for supplying voltages and the other two are earthing planes. This arrangement makes it possible to mount, on the upper layer which carries the various components of the computer, up to eight connectors J1-J8 to which other printed-circuit boards controlling various input/output devices may be connected. Seven of the connectors J1-J7 are connected to a conventional I/O bus, whereas the eighth, J8, is connected to certain of the lines of the I/O bus and to certain of the lines of the internal bus of the board.
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