公开(公告)号：CA2107046A1

公开(公告)日：1994-07-09

申请号：CA2107046

申请日：1993-09-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D

IPC: G06F9/38 ,  G06F9/30

Abstract: A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.

公开(公告)号：CA2159888A1

公开(公告)日：1996-04-06

申请号：CA2159888

申请日：1995-10-04

Applicant: IBM ,  MOTOROLA INC

Inventor： ROSSBACH PAUL C ,  KAU CHIN-CHENG ,  LEVITAN DAVID S

IPC: G06F9/32 ,  G06F9/355 ,  G06F9/38

Abstract: An improved method of addressing within a pipelined processor having an address bit width of m + n bits is disclosed, which includes storing m high order bits corresponding to a first range of addresses, which encompasses a selected plurality of data executing within the pipelined processor. The n low order bits of addresses associated with each of the selected plurality of data are also stored. After determining the address of a subsequent datum to be executed within the processor, the subsequent datum is fetched. In response to fetching a subsequent datum having an address outside of the first range of addresses, a status register is set to a first of two states to indicate that an update to the first address register is required. In response to the status register being set to the second of the two states, the subsequent datum is dispatched for execution within the pipelined processor. The n low order bits of the subsequent datum are then stored, such that memory required to store addresses of instructions executing within the pipelined processor is thereby decreased.