公开(公告)号：JP2009048633A

公开(公告)日：2009-03-05

申请号：JP2008207408

申请日：2008-08-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEVITAN DAVID S ,  SPEIGHT WILLIAM E ,  ZHANG LIXIN

IPC: G06F9/38

CPC classification number: G06F9/3804 ,  G06F9/3844

Abstract: PROBLEM TO BE SOLVED: To provide a processor with a branch target address cache and a data processing method.
SOLUTION: An instruction sequencing logic 13 for fetching instructions from a memory system 12 comprises a branch logic 36 for outputting predicted branch target addresses for use as instruction fetch addresses. The branch logic 36 comprises a level one branch target address cache (BTAC) and a level two BTAC, and each BTAC entry associates at least a tag with a predicted branch target address. The branch logic evaluates the level one and level two BTACs in parallel with a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC for use as a second instruction fetch address in a first clock cycle and a second predicted branch target address from the level two BTAC for use as a third instruction fetch address in a second clock cycle.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为处理器提供分支目标地址高速缓存和数据处理方法。 解决方案：用于从存储器系统12获取指令的指令排序逻辑13包括用于输出用作指令获取地址的预测分支目标地址的分支逻辑36。 分支逻辑36包括一级分支目标地址高速缓存（BTAC）和二级BTAC，并且每个BTAC条目将至少一个标签与预测的分支目标地址相关联。 分支逻辑与第一指令获取地址的标签部分并行地评估一级和二级BTAC，以从第一级BTAC获得第一预测分支目标地址，以在第一时钟周期中用作第二指令获取地址;以及 来自第二级BTAC的第二预测分支目标地址，用作第二时钟周期中的第三指令获取地址。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2004326752A

公开(公告)日：2004-11-18

申请号：JP2004111504

申请日：2004-04-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEVITAN DAVID S ,  BARARAMU SHINHAROI

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30189 ,  G06F9/3851

Abstract: PROBLEM TO BE SOLVED: To provide a method and circuit for structuring an SMT (simultaneous multithread) system so that execution of a single thread is optimized in addition to a multithread mode.
SOLUTION: Instructions are alternately selected from two threads every clock cycle and loaded into an IFAR (Instruction Fetch Address Register) 103. If a branch instruction estimated to success is detected, in a single thread mode a calculated address from a branch prediction logical circuit 203 is loaded into the IFAR 103 on the next clock cycle. In an SMT mode, if the branch instruction is detected, a selected instruction address is loaded into the IFAR 103 on the next cycle. A calculated address is fed back and loaded into the IFAR 103 in a second clock cycle that follows. Feedback delay effectively switches a pipeline from three stages to four stages.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：DE69321698T2

公开(公告)日：1999-06-10

申请号：DE69321698

申请日：1993-12-27

Applicant: IBM

Inventor： LEVITAN DAVID S

IPC: G06F9/38

Abstract: In a superscalar processor system which is capable of accessing multiple instructions simultaneously, a branch history table (60) is established which includes a predictive field (62-76) for each possible instruction fetch position within a multi-instruction access. Each group of predictive fields (62-76) is accessed within the branch history table (60) utilizing a portion of the instruction fetch address (56,58). A particular predictive field (62-76) within the group is then selected which corresponds to the position of the branch instruction within the instruction fetch. The content of the selected predictive field (62-76) is then utilized to predict whether or not a branch is taken for the corresponding branch instruction. Each predictive field (62-76) preferably comprises a two bit binary counter which is incremented or decremented in response to a branch being "taken" or "not taken".

公开(公告)号：DE69322064D1

公开(公告)日：1998-12-17

申请号：DE69322064

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：DE69325086T2

公开(公告)日：1999-12-16

申请号：DE69325086

申请日：1993-12-27

Applicant: IBM

Inventor： LEVITAN DAVID S

IPC: G06F9/32 ,  G06F9/38

Abstract: A data processing system executing speculative instructions includes a memory for storing instructions at addresses, count registers (42, 44, 46) for storing an update value, a dispatch version value and a completion version value. A fetcher connected to a branch unit fetches instructions from memory based upon addresses calculated by the branch unit, which handles processing of conditional branch instructions. Further included are means (60) responsive to completion of initialization for copying the update value as the completion version value and means (52) responsive to dispatch of a conditional branch instruction. Means (62) responsive to completion of the branch provide for decrementing contents of a completion version register. Finally, means (58) responsive to occurrence of an interrupt prior to completion of the branch provide for replacing the dispatch version value with the completion version value to restore the system to a state prior to the speculative execution of instructions.

公开(公告)号：DE69325086D1

公开(公告)日：1999-07-01

申请号：DE69325086

申请日：1993-12-27

Applicant: IBM

Inventor： LEVITAN DAVID S

IPC: G06F9/32 ,  G06F9/38

Abstract: A data processing system executing speculative instructions includes a memory for storing instructions at addresses, count registers (42, 44, 46) for storing an update value, a dispatch version value and a completion version value. A fetcher connected to a branch unit fetches instructions from memory based upon addresses calculated by the branch unit, which handles processing of conditional branch instructions. Further included are means (60) responsive to completion of initialization for copying the update value as the completion version value and means (52) responsive to dispatch of a conditional branch instruction. Means (62) responsive to completion of the branch provide for decrementing contents of a completion version register. Finally, means (58) responsive to occurrence of an interrupt prior to completion of the branch provide for replacing the dispatch version value with the completion version value to restore the system to a state prior to the speculative execution of instructions.

公开(公告)号：DE69322064T2

公开(公告)日：1999-07-01

申请号：DE69322064

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：DE69321698D1

公开(公告)日：1998-11-26

申请号：DE69321698

申请日：1993-12-27

Applicant: IBM

Inventor： LEVITAN DAVID S

IPC: G06F9/38

Abstract: In a superscalar processor system which is capable of accessing multiple instructions simultaneously, a branch history table (60) is established which includes a predictive field (62-76) for each possible instruction fetch position within a multi-instruction access. Each group of predictive fields (62-76) is accessed within the branch history table (60) utilizing a portion of the instruction fetch address (56,58). A particular predictive field (62-76) within the group is then selected which corresponds to the position of the branch instruction within the instruction fetch. The content of the selected predictive field (62-76) is then utilized to predict whether or not a branch is taken for the corresponding branch instruction. Each predictive field (62-76) preferably comprises a two bit binary counter which is incremented or decremented in response to a branch being "taken" or "not taken".

公开(公告)号：AT173345T

公开(公告)日：1998-11-15

申请号：AT93120943

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：CA2107304A1

公开(公告)日：1994-07-09

申请号：CA2107304

申请日：1993-09-29

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  TU PAUL K ,  WALDECKER DONALD E

IPC: G06F9/38 ,  G06F15/16

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.