中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.018 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE69322064D1

    公开(公告)日：1998-12-17

    申请号：DE69322064

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

    METHOD AND SYSTEM OF ADDRESSING
    3.
    发明专利
    METHOD AND SYSTEM OF ADDRESSING 未知

    公开(公告)号：CA2159888A1

    公开(公告)日：1996-04-06

    申请号：CA2159888

    申请日：1995-10-04

    Applicant: IBM ,  MOTOROLA INC

    Inventor： ROSSBACH PAUL C ,  KAU CHIN-CHENG ,  LEVITAN DAVID S

    IPC: G06F9/32 ,  G06F9/355 ,  G06F9/38

    Abstract: An improved method of addressing within a pipelined processor having an address bit width of m + n bits is disclosed, which includes storing m high order bits corresponding to a first range of addresses, which encompasses a selected plurality of data executing within the pipelined processor. The n low order bits of addresses associated with each of the selected plurality of data are also stored. After determining the address of a subsequent datum to be executed within the processor, the subsequent datum is fetched. In response to fetching a subsequent datum having an address outside of the first range of addresses, a status register is set to a first of two states to indicate that an update to the first address register is required. In response to the status register being set to the second of the two states, the subsequent datum is dispatched for execution within the pipelined processor. The n low order bits of the subsequent datum are then stored, such that memory required to store addresses of instructions executing within the pipelined processor is thereby decreased.

    6.
    发明专利
    未知

    公开(公告)号：DE69321929T2

    公开(公告)日：1999-07-01

    申请号：DE69321929

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having intermediate storage buffers (60), general purpose registers (62), and a storage buffer index (58). A particular storage buffer (60) is assigned to a destination operand within a selected multiple scalar instruction. A relationship between the particular intermediate storage buffer (60) and a designated general purpose register (62) is stored in the storage buffer index (58) when the instruction which has been dispatched is replaced in the dispatcher by another instruction. Results of execution from the selected multiple scalar instruction are stored in the particular intermediate storage buffer (60) when the selected instruction is executed. The storage buffer index (58) is used to determine which storage buffers (60) to use as source operands for those instructions which are dispatched between the time that a storage buffer (58) has been assigned for a specific general purpose register (62) and the results of execution are moved from the storage buffer (60) into the general purpose register (62).

    7.
    发明专利
    未知

    公开(公告)号：AT173100T

    公开(公告)日：1998-11-15

    申请号：AT93120933

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having intermediate storage buffers (60), general purpose registers (62), and a storage buffer index (58). A particular storage buffer (60) is assigned to a destination operand within a selected multiple scalar instruction. A relationship between the particular intermediate storage buffer (60) and a designated general purpose register (62) is stored in the storage buffer index (58) when the instruction which has been dispatched is replaced in the dispatcher by another instruction. Results of execution from the selected multiple scalar instruction are stored in the particular intermediate storage buffer (60) when the selected instruction is executed. The storage buffer index (58) is used to determine which storage buffers (60) to use as source operands for those instructions which are dispatched between the time that a storage buffer (58) has been assigned for a specific general purpose register (62) and the results of execution are moved from the storage buffer (60) into the general purpose register (62).

    METHOD AND SYSTEM FOR INDEXING THE ASSIGNMENT OF INTERMEDIATE STORAGE BUFFERS IN A SUPERSCALAR PROCESSOR SYSTEM
    9.
    发明专利
    METHOD AND SYSTEM FOR INDEXING THE ASSIGNMENT OF INTERMEDIATE STORAGE BUFFERS IN A SUPERSCALAR PROCESSOR SYSTEM 未知

    公开(公告)号：CA2112995A1

    公开(公告)日：1994-07-09

    申请号：CA2112995

    申请日：1994-01-06

    Applicant: IBM

    Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

    IPC: G06F9/38 ,  G06F9/30

    Abstract: METHOD AND SYSTEM FOR INDEXING THE ASSIGNMENT OF INTERMEDIATE STORAGE BUFFERS IN A SUPERSCALAR PROCESSOR SYSTEM A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having a plurality of intermediate storage buffers, a plurality of general purpose registers, and a storage buffer index. Multiple scalar instructions may be simultaneously dispatched from a dispatch buffer to a plurality of execution units. Each of the multiple scalar instructions generally include at least one source operand and one destination operand. A particular one of the plurality of intermediate storage buffers is assigned to a destination operand within a selected one of the multiple scalar instructions. A relationship between the particular one of the plurality of intermediate storage buffers and a designated one of the plurality of general purpose registers is stored in the storage buffer index at that time when the instruction which has been dispatched is replaced in the dispatcher by another instruction in the application program sequence. Results of execution from the selected one of the multiple scalar instructions are stored in the particular one of the intermediate storage buffers when the selected instruction is executed. The storage buffer index is used to determine which storage buffers to use as source operands for those instructions which are dispatched between the time that a storage buffer has been assigned for a specific general purpose register and the results of execution are moved from the storage buffer into the general purpose register.

    METHOD AND SYSTEM FOR INCREASED INSTRUCTION SYNCHRONIZATION EFFICIENCY IN A SUPERSCALAR PROCESSOR SYSTEM
    10.
    发明专利
    METHOD AND SYSTEM FOR INCREASED INSTRUCTION SYNCHRONIZATION EFFICIENCY IN A SUPERSCALAR PROCESSOR SYSTEM 未知

    公开(公告)号：CA2107045A1

    公开(公告)日：1994-07-09

    申请号：CA2107045

    申请日：1993-09-27

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A method and system for increased instruction synchronization efficiency in a superscalar processor system which includes instructions having multiple source and destination operands. Simultaneous dispatching of multiple instructions creates a source-to-destination data dependency problem in that the results of one instruction may be necessary to accomplish execution of a second instruction. Data dependency hazards may be eliminated by prohibiting each instruction from dispatching until all possible data dependencies have been eliminated by the completion of preceding instructions; however, instruction dispatch efficiency is substantially decrease d utilizing this technique. Data dependency interlock circuitry may be utilized to clear possible data dependency hazards; however, the complexity of such circuitry increases dramatically as the number of interlocked sources and destinations increases. The method and system of the present invention utilizes data dependency interlock circuitry capable of interlocking two source operands by two destination operands for each instruction. Instructions having three or more source operands are interlocked at the dispatch stage for the first two source operands utilizing existing data dependency interlock circuitry. Thereafter, the instruction is dispatched only after data dependency hazards are cleared for the first two source operands, utilizing the data dependency interlock circuitry, and all instructions preceding the instruction have been completed, eliminating possible data dependency hazards for the third source operand. In this manner, instructions which include three source operands may be synchronized without requiring a substantial increase in data dependency interlock circuitry and with only a slight degradation in system efficiency.

Patent Agency Ranking