公开(公告)号：BR9203849A

公开(公告)日：1993-05-04

申请号：BR9203849

申请日：1992-10-02

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HOFMANN RICHARD GERARD ,  LOHMAN TERENCE J

IPC: G06F13/00 ,  G06F11/00 ,  G06F11/14 ,  G06F11/20 ,  G06F13/28 ,  G06F12/00

Abstract: A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.

公开(公告)号：BR9203650A

公开(公告)日：1993-04-27

申请号：BR9203650

申请日：1992-09-18

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  LOHMAN TERENCE J ,  BRANNON SHERWOOD ,  CONCILIO IAN A ,  HOFMANN RICHARD G

IPC: G06F13/00

公开(公告)号：CA2071306A1

公开(公告)日：1993-04-16

申请号：CA2071306

申请日：1992-06-16

Applicant: IBM

Inventor： BOURY BECHARA F ,  LOHMAN TERENCE J ,  NGUYEN LONG D

IPC: G06F13/18 ,  G06F13/30 ,  G06F13/362

Abstract: An arbiter with first and second CPU timers is provided which advantageously allows measuring and controlling CPU bus ownership intervals via the arbiter. The first CPU timer, a running timer, specifies the total interval that the CPU is allocated the bus. The second timer, an idle timer, specifies an interval which the CPU may own the bus without performing an operation. The arbiter uses these two timers to dynamically adjust and control CPU bus ownership.

公开(公告)号：CA2071301A1

公开(公告)日：1993-04-16

申请号：CA2071301

申请日：1992-06-16

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HOFMANN RICHARD G ,  LOHMAN TERENCE J

IPC: G06F13/00 ,  G06F11/00 ,  G06F11/14 ,  G06F11/20 ,  G06F13/28 ,  G06F13/12

Abstract: BC9-91-079 ERROR DETECTION AND RECOVERY IN A DMA CONTROLLER A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.