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公开(公告)号：DE3786125T2
公开(公告)日：1993-12-02
申请号：DE3786125
申请日：1987-06-26
Applicant: IBM
Inventor： LUMELSKY LEON
Abstract: A display controller provides multiple different resolutions by selectively enabling different combinations of shift registers (SHR0-SHR7) between the frame buffer and video look-up tables (VLTs). The VLTs are partitioned, with different partitions being programmed identically in accordance with the values of only the number of address bits which will be active from the shift registers at any one time. For example, reading out any of the 512 lines of the frame buffer twice in succession, before incrementing the line counter to access the next line, allows for using one half of the stored bits each time such line is read, to simulate a horizontal resolution having the double number of pixels. Alternatively, making two consecutive passes through the buffer and using each time a different half of the stored bits, allows for simulating a vertical resolution comprising the double number of display lines.
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公开(公告)号：CA2068001C
公开(公告)日：1999-03-02
申请号：CA2068001
申请日：1992-05-05
Applicant: IBM
Inventor： LUMELSKY LEON , CHOI SUNG M , PEEVERS ALAN W , PITTAS JOHN L
IPC: G09G5/00 , G06F12/00 , G09G5/02 , G09G5/14 , G09G5/36 , G09G5/39 , G09G5/391 , G09G5/395 , H04N7/01 , G09G1/16
Abstract: An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.
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公开(公告)号：DE69225538T2
公开(公告)日：1999-02-04
申请号：DE69225538
申请日：1992-07-03
Applicant: IBM
Inventor： CHOI SUNG MIN , LUMELSKY LEON , PEEVERS ALAN WESLEY , PITTAS JOHN LOUIS
IPC: G09G5/00 , G06F12/00 , G09G5/02 , G09G5/14 , G09G5/36 , G09G5/39 , G09G5/391 , G09G5/395 , H04N7/01
Abstract: An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.
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公开(公告)号：DE69123883D1
公开(公告)日：1997-02-13
申请号：DE69123883
申请日：1991-05-15
Applicant: IBM
Inventor： LUMELSKY LEON
IPC: G06F3/153 , G09G5/00 , G09G5/36 , G09G5/39 , G09G5/391 , G09G5/393 , G09G5/395 , G09G5/397 , G09G5/399 , H04N5/262 , H04N5/44
Abstract: Image conversion method and apparatus that provides for (a) storing in a first memory a first image field; (b) storing in a second memory a second image field; (c) reading the first and the second memories; (d) simultaneously displaying on a display screen the first and the second image fields as a single image frame; and (e) while performing the step of reading the method includes a step of storing in a third memory a third image field. The first, second and third memories are provided as a frame buffer having a 3x3 memory block organization. For image fields numbered 1, 2, 3, 4, 5...n.. the system of the invention reads the image fields two at a time in accordance with a predetermined sequence given by: 1 and 2, 2 and 3, 3 and 4, 4 and 5, ... (n - 1) and n, n and (n + 1). A high resolution frame length is selected to be longer than or shorter than a television field period. The phase difference between the two is measured and circuitry alters the predetermined read-out sequence to ensure that a field memory to be read will not also be required for simultaneously storing a next television field.
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公开(公告)号：DE69211447T2
公开(公告)日：1996-12-05
申请号：DE69211447
申请日：1992-07-02
Applicant: IBM
Inventor： CHOI SUNG MIN , LUMELSKY LEON , PEEVERS ALAN WESLEY , PITTAS JOHN LOUIS
Abstract: A display system is described which includes storage for receiving a compressed pixel image manifesting at least a pair of encoded colors and a bit MASK that defines which pixels of a pixel subset of the pixel image receive one of the colors. The system comprises a plurality of memory modules (34). The pixels in the subset are interleaved in the memory modules. A generator is provided for applying signals to cause data to be written into each of modules in parallel. Register means are provided for applying data manifesting the encoded colors to the modules. Control apparatus is responsive to the MASK bits for controlling the generator to write the encoded color data, in parallel and in a single memory cycle, into all pixel positions of the subset that are designated for the color(s) by MASK bit position values.
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Patent Agency Ranking
公开(公告)号：DE69210243D1
公开(公告)日：1996-05-30
申请号：DE69210243
申请日：1992-06-15
Applicant: IBM
Inventor： CHOI SUNG , LUMELSKY LEON , PEEVERS ALAN , PITTAS JOHN
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公开(公告)号：DE3852045T2
公开(公告)日：1995-05-24
申请号：DE3852045
申请日：1988-01-26
Applicant: IBM
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公开(公告)号：DE69015536D1
公开(公告)日：1995-02-09
申请号：DE69015536
申请日：1990-06-05
Applicant: IBM
Inventor： LUMELSKY LEON , PEEVERS ALAN W , CHOI SUNG MIN
IPC: H04N5/66 , G06T3/40 , G09G5/00 , G09G5/02 , G09G5/14 , G09G5/36 , H04N1/393 , H04N5/262 , H04N7/01 , H04N3/22 , G06T3/60 , G09G1/00
Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor. According to a preferred embodiment of the invention the expansion circuit functions to modify the controi signals which controls the read-out of the frame buffer in a predetermined fashion without any additional video buffer storage means. In the simplest form of the invention the additional circuitry required comprises only two registers for holding the generated expansion patterns in the horizontal and vertical direction and two shift registers for receiving these patterns and processing same to alter the frame buffer clocks to achieve replication of predetermined lines and pixels as determined from the said expansion pattern.
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公开(公告)号：SK6694A3
公开(公告)日：1994-07-06
申请号：SK6694
申请日：1992-06-15
Applicant: IBM
Inventor： CHOI SUNG MIN , LUMELSKY LEON , PEEVERS ALAN , PITTAS JOHN L
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公开(公告)号：CA2068001A1
公开(公告)日：1993-01-23
申请号：CA2068001
申请日：1992-05-05
Applicant: IBM
Inventor： LUMELSKY LEON , CHOI SUNG M , PEEVERS ALAN W , PITTAS JOHN L
IPC: G09G5/00 , G06F12/00 , G09G5/02 , G09G5/14 , G09G5/36 , G09G5/39 , G09G5/391 , G09G5/395 , H04N7/01 , G09G1/16
Abstract: An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.
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