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    COMPLEMENTARY TRANSISTOR STRUCTURE AND METHOD FOR MANUFACTURE
    11.
    发明专利
    COMPLEMENTARY TRANSISTOR STRUCTURE AND METHOD FOR MANUFACTURE 未知

    公开(公告)号：CA1142267A

    公开(公告)日：1983-03-01

    申请号：CA365496

    申请日：1980-11-26

    Applicant: IBM

    Inventor： MAGDO INGRID E ,  RUPPRECHT HANS S

    IPC: H01L21/225 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/082 ,  H01L29/08 ,  H01L29/73 ,  H01L21/22

    Abstract: Complementary Transistor Structure and Method for Manufacture Complementary, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics. A method for fabricating such complementary devices is also provided. In the method, a barrier region of a first conductivity type is formed on the surface of the monocrystalline semiconductor substrate doped with a second conductivity type. After an annealing heat treatment to drive in the doping ions of the barrier region, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. The collector region for the other complementary transistor is formed within at least one other isolation region. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. To provide improved PNP transistor performance, the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer. FI 9-79-077

    FABRICATING HIGH PERFORMANCE INTEGRATED BIPOLAR AND COMPLEMENTARY FIELD EFFECT TRANSISTORS
    12.
    发明专利
    FABRICATING HIGH PERFORMANCE INTEGRATED BIPOLAR AND COMPLEMENTARY FIELD EFFECT TRANSISTORS 未知

    公开(公告)号：CA1048656A

    公开(公告)日：1979-02-13

    申请号：CA255057

    申请日：1976-06-16

    Applicant: IBM

    Inventor： MAGDO INGRID E ,  MAGDO STEVEN

    IPC: H01L29/78 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/73 ,  H01L27/02 ,  H01L29/72 ,  H01L21/70

    Abstract: FABRICATING HIGH PERFORMANCE INTEGRATED BIPOLAR AND COMPLEMENTARY FIELD EFFECT TRANSISTORS A method for making dielectrically isolated bipolar and field effect transistors in the same substrate and a semiconductor integrated circuit so-made. The method consists of forming a first region of one conductivity type in a monocrystalline semiconductor substrate on a first type, forming second and third regions having different diffusion rates in the substrate, forming a monocrystalline layer of the other conductivity type, adding impurity to the second region, depositing a dielectric layer over the monocrystalline layer, forming openings in the dielectric layer over the first and third regions and another location in the monocrystalline layer, and depositing a layer of silicon over the dielectric layer and the openings. The impurities in the third region are outdiffused into the monocrystalline region over it to form the channel region of a Field Effect transistor. The regions of the layer of silicon are dielectrically isolated from one another and emitter and base regions of a bipolar transistor are selectively formed in the monocrystalline region over subcollector regions. Source and drain regions for a field effect transistor are formed over the third region and the another location to form both channel types of field effect transistors.

    14.
    发明专利
    未知

    公开(公告)号：FR2308203A1

    公开(公告)日：1976-11-12

    申请号：FR7605923

    申请日：1976-02-25

    Applicant: IBM

    Inventor： MAGDO INGRID E ,  MAGDO STEVEN ,  NESTORK WILLIAM J

    IPC: H01L27/00 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L23/535

    Abstract: A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide.

    SELF-ALIGNED METAL PROCESS FOR FIELD EFFECT TRANSISTOR INTEGRATED CIRCUITS
    16.
    发明专利
    SELF-ALIGNED METAL PROCESS FOR FIELD EFFECT TRANSISTOR INTEGRATED CIRCUITS 未知

    公开(公告)号：CA1169585A

    公开(公告)日：1984-06-19

    申请号：CA379794

    申请日：1981-06-15

    Applicant: IBM

    Inventor： ABBAS SHAKIR A ,  MAGDO INGRID E

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L29/41 ,  H01L29/76

    Abstract: SELF-ALIGNED METAL PROCESS FOR FIELD EFFECT TRANSISTOR INTEGRATED CIRCUITS A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer is then FI9-80-016 removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions and form the gate electrodes. A blanket layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached. The plastic material is then removed leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed. FI9-80-016

    METHOD FOR FORMING INTEGRATED CIRCUIT REGIONS DEFINED BY RECESSED DIELECTRIC ISOLATION
    17.
    发明专利
    METHOD FOR FORMING INTEGRATED CIRCUIT REGIONS DEFINED BY RECESSED DIELECTRIC ISOLATION 未知

    公开(公告)号：CA1045724A

    公开(公告)日：1979-01-02

    申请号：CA250193

    申请日：1976-04-13

    Applicant: IBM

    Inventor： MAGDO INGRID E

    IPC: H01L21/76 ,  H01L21/00 ,  H01L21/283 ,  H01L21/32 ,  H01L21/762 ,  H01L23/485 ,  B01J17/00

    Abstract: A METHOD FOR FORMING INTEGRATED CIRCUIT REGIONS DEFINED BY RECESSED DIELECTRIC ISOLATION In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a silicon substrate comprising initially introducing conductivity-determining impurities into the substrate to form at least one region of one-type conductivity at the surface of said substrate. Then, a mask comprising a composite of a bottom layer of silicon dioxide and a top layer of silicon nitride is formed over at least a portion of the surface of said introduced regions. The substrate is then subsequently thermally oxidized to an extent sufficient to form regions of recessed silicon dioxide abutting and thus laterally defining said region of one-type conductivity. In this manner, it is ensured that the recessed silicon dioxide will abut introduced region irrespective of the extent of the "bird's beak" normally associated with thermal oxidation utilizing silicon dioxide-silicon nitride masking.

    INTEGRATED CIRCUIT CHIP CARRIER AND METHOD FOR FORMING THE SAME
    18.
    发明专利
    INTEGRATED CIRCUIT CHIP CARRIER AND METHOD FOR FORMING THE SAME 未知

    公开(公告)号：CA1026469A

    公开(公告)日：1978-02-14

    申请号：CA223173

    申请日：1975-03-21

    Applicant: IBM

    Inventor： MAGDO INGRID E ,  MAGDO STEVEN

    IPC: H05K3/46 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L

    Abstract: An integrated circuit chip carrier with multi-level metallurgy, in which the effects of the metallurgy in causing elevation irregularitiies at the various levels of the structure are minimized, is produced by a method wherein a first plurality of levels of metallization patterns respectively separated by layers of dielectric material are first formed on a planar primary layer supported on a temporary substrate having a chemical etchability different from that of the layer. The primary layer is electrically insulative with respect to said metallization patterns. Then, a supporting layer is formed on the uppermost covering layer, after which the substrate is removed with a chemical etchant which preferentially etches the substrate away from the insulative layer. Next, an opposite plurality of levels of metallization patterns are formed on the side of the insulative layer opposite to the first formed metallization patterns. These opposite metallization patterns are also respectively separated by covering layers of dielectric material.

    19.
    发明专利
    未知

    公开(公告)号：FR2315169A1

    公开(公告)日：1977-01-14

    申请号：FR7615006

    申请日：1976-05-13

    Applicant: IBM

    Inventor： MAGDO INGRID E ,  MAGDO STEVEN

    IPC: H01L29/78 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/73 ,  H01L21/72 ,  H01L27/04

    Abstract: A method for fabricating both bipolar as well as complementary MOS field effect transistors, i.e., BI-CMOS transistors in the same semiconductor substrate. The preferred embodiment of the method provides bipolar and CMOS transistors having breakdown voltages (BVceo) in excess of 10 volts and CMOS devices having no latchup problems, with a minimum number of processing steps. The method also contemplates the formation of auxiliary devices such as resistors and Schottky Barrier diodes.

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