公开(公告)号：US3506969A

公开(公告)日：1970-04-14

申请号：US3506969D

申请日：1967-04-04

Applicant: IBM

Inventor： ABBAS SHAKIR A

IPC: G11C17/00 ,  G11C17/04 ,  G11C5/02

CPC classification number: G11C17/00 ,  G11C17/04

公开(公告)号：FR2333348A1

公开(公告)日：1977-06-24

申请号：FR7632452

申请日：1976-10-18

Applicant: IBM ,  IBM

Inventor： ABBAS SHAKIR A ,  DOCKERTY ROBERT C ,  SHAKIR A ABBAS ET ROBERT C DOCKERTY

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/283 ,  H01L21/76 ,  H01L21/8247 ,  H01L29/41 ,  H01L29/43 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/31

公开(公告)号：CA1023859A

公开(公告)日：1978-01-03

申请号：CA194527

申请日：1974-03-08

Applicant: IBM

Inventor： ABBAS SHAKIR A ,  BARILE CONRAD A ,  LANE RALPH D ,  LIU PETER T

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/417 ,  H01L29/788 ,  H01L29/792 ,  H01L29/40

Abstract: A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.

公开(公告)号：FR2308202A1

公开(公告)日：1976-11-12

申请号：FR7605144

申请日：1976-02-17

Applicant: IBM

Inventor： ABBAS SHAKIR A ,  DOCKERTY ROBERT C ,  POPONIAK MICHAEL R

IPC: H01L21/306 ,  H01L21/3063 ,  H01L21/308 ,  H01L21/322 ,  H01L29/06 ,  B41J3/04

Abstract: 1515031 Electrolytic etching of silicon INTERNATIONAL BUSINESS MACHINES CORP 3 Feb 1976 [14 April 1975] 4111/76 Heading C7B [Also in Division H1] A hole is made in a monocrystalline silicon body by providing masking with aligned apertures on parallel opposed faces of the body, providing a conductor in contact with the body through one of the openings and using this as anode in an anodic treatment to convert the entire region between the apertures to porous silicon which is then etched out to leave a hole. Typically a plurality of holes are simultaneously formed in a 100 oriented wafer which may have integrated circuitry formed on one or both faces. The masking may consist of silicon dioxide or nitride with an optical overlayer of chromium, or of silicon oxynitride or nitride-onoxide. After photoetching to form the apertures heavily doped surface regions may be formed below the apertures on one or both faces by impurity diffusion or implantation of helium ions or protons and a chromium anode layer deposited on one face. After anodic treatment in a 1:2 mixture of 49% hydrofluoric acid and distilled water the anode is removed and the porous silicon etched out.

公开(公告)号：CA961582A

公开(公告)日：1975-01-21

申请号：CA151675

申请日：1972-09-14

Applicant: IBM

Inventor： ABBAS SHAKIR A ,  STERN PAUL G

IPC: G11C17/06 ,  G11C11/30 ,  G11C16/02 ,  G11C17/14 ,  H01L23/525

Abstract: An electronically rewritable read-only memory comprising an integrated semiconductor array of P-N junctions formed in a semiconductor substrate. A dielectric film is formed on the surface of the substrate on top of which a thin metallic film is deposited. The dielectric is thinner above an active region of each of the junctions than it is above the other regions of the substrate. When a suitable voltage is applied across the metallic film and dielectric, the metallic film diffuses through the dielectric film at the thinner areas, thereby forming ohmic via connections with the active junction regions. At the same time, the dielectric "self-heals" i.e., the via connections are disconnected from the metallic film around the periphery of the thin areas of the dielectric. A second layer of metallization over the metallic film establishes conductive contact between the layer and the active junction region. The contacts can be broken at selected junctions by passing a current through the diffused metallization. The contacts can be reestablished at selected junctions by applying a suitable healing voltage across the metallic film and the dielectric.

公开(公告)号：FR2367349A1

公开(公告)日：1978-05-05

申请号：FR7725999

申请日：1977-08-19

Applicant: IBM

Inventor： ABBAS SHAKIR A ,  DOCKERTY ROBERT CH

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L21/76 ,  H01L27/04

公开(公告)号：CA1005925A

公开(公告)日：1977-02-22

申请号：CA173051

申请日：1973-06-04

Applicant: IBM

Inventor： ABBAS SHAKIR A ,  CHANG CHI S ,  FREEMAN LEO B JR ,  KNEPPER RONALD W

IPC: H01L27/10 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/535 ,  H01L27/108 ,  H01L29/06

公开(公告)号：CA1169585A

公开(公告)日：1984-06-19

申请号：CA379794

申请日：1981-06-15

Applicant: IBM

Inventor： ABBAS SHAKIR A ,  MAGDO INGRID E

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L29/41 ,  H01L29/76

Abstract: SELF-ALIGNED METAL PROCESS FOR FIELD EFFECT TRANSISTOR INTEGRATED CIRCUITS A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer is then FI9-80-016 removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions and form the gate electrodes. A blanket layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached. The plastic material is then removed leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed. FI9-80-016

公开(公告)号：CA1079864A

公开(公告)日：1980-06-17

申请号：CA286133

申请日：1977-09-06

Applicant: IBM

Inventor： ABBAS SHAKIR A ,  DOCKERTY ROBERT C

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L21/70

Abstract: PROCESS FOR MAKING FIELD EFFECT AND BIPOLAR TRANSISTORS ON THE SAME SEMICONDUCTOR CHIP A process and the resulting structure for making metal oxide silicon field effect transistors and vertical bipolar transistors on the same semiconductor chip with the devices being dielectrically isolated from each other. The process does not require an epitaxial layer. The bipolar devices have utility as cross-chip or offchip drivers or can be utilized for analog circuitry.

公开(公告)号：CA1061014A

公开(公告)日：1979-08-21

申请号：CA266616

申请日：1976-11-26

Applicant: IBM

Inventor： ABBAS SHAKIR A ,  DOCKERTY ROBERT C

IPC: H01L21/283 ,  H01L21/28 ,  H01L21/314 ,  H01L21/76 ,  H01L21/8247 ,  H01L29/41 ,  H01L29/43 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  B05D5/12 ,  H01L29/76

Abstract: FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD FOR MAKING SAME An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.