公开(公告)号：US3349476A

公开(公告)日：1967-10-31

申请号：US32609163

申请日：1963-11-26

Applicant: IBM

Inventor： PILKUHN MANFRED H ,  RUPPRECHT HANS S

IPC: H01L21/288 ,  H01L33/00 ,  H01L33/38

CPC classification number: H01L33/38 ,  H01L21/288 ,  H01L33/0062

公开(公告)号：US3600240A

公开(公告)日：1971-08-17

申请号：US3600240D

申请日：1968-12-12

Applicant: IBM

Inventor： RUPPRECHT HANS S ,  WOODALL JERRY M

IPC: H01L21/208 ,  H01L33/00 ,  H01L7/38

CPC classification number: H01L33/00 ,  H01L21/02395 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/02625 ,  H01L21/02628 ,  Y10S438/915 ,  Y10S438/955

Abstract: P-TYPE GALLIUM ARSENIDE IS GROWN EPITAXIALLY FROM SOLUTION IN GALLIUM ON THE SURFACE OF N-TYPE GALLIUM ARSENIDE, WITH SILICON AS DOPANT ON BOTH SIDE OF THE JUNCTION. A RECOMBINATION RADIATION DEVICE IS MADE BY THE METHOD.

公开(公告)号：CA886237A

公开(公告)日：1971-11-16

申请号：CA886237D

Applicant: IBM

Inventor： WOODALL JERRY M ,  RUPPRECHT HANS S

公开(公告)号：CA1180256A

公开(公告)日：1985-01-02

申请号：CA371106

申请日：1981-02-17

Applicant: IBM

Inventor： RUPPRECHT HANS S ,  WOODALL JERRY M

IPC: H01L21/265 ,  H01L21/324 ,  C30B33/00

Abstract: ANNEALING OF ION IMPLANTED III-V COMPOUNDS Thermal decomposition is reduced and stoichiometry is retained during annealing of a multiple element intermetallic semiconductor material by heating it in an environment with an excess of the most volatile constituent. In particular, a GaAs wafer is annealed with a surface into which Si has been implanted while the surface is in proximity to InAs.

公开(公告)号：CA1106981A

公开(公告)日：1981-08-11

申请号：CA312414

申请日：1978-09-29

Applicant: IBM

Inventor： HORNG CHENG T ,  MICHEL ALWIN E ,  RUPPRECHT HANS S ,  SCHWENKER ROBERT O

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/265 ,  H01L21/331 ,  H01L21/76

Abstract: IMPROVED PROCESS FOR PRODUCING INTEGRATED CIRCUIT DEVICES BY ION IMPLANTATION In this process of producing a bipolar transistor, all the regions of the device except the emitter region are formed by ion implantation through an inorganic dielectric layer of uniform thickness. Subsequently, all the contact openings to the emitter, base and collector are formed and the emitter is implanted through the emitter contact opening. This unique combination of process steps permits the use of a surface insulating dielectric layer of uniform thickness, wherein all capacitances are uniform and controllable while still permitting direct implantation of the emitter, which, because of its shallow depth is difficult to implant through an oxide.

公开(公告)号：CA1142267A

公开(公告)日：1983-03-01

申请号：CA365496

申请日：1980-11-26

Applicant: IBM

Inventor： MAGDO INGRID E ,  RUPPRECHT HANS S

IPC: H01L21/225 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/082 ,  H01L29/08 ,  H01L29/73 ,  H01L21/22

Abstract: Complementary Transistor Structure and Method for Manufacture Complementary, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics. A method for fabricating such complementary devices is also provided. In the method, a barrier region of a first conductivity type is formed on the surface of the monocrystalline semiconductor substrate doped with a second conductivity type. After an annealing heat treatment to drive in the doping ions of the barrier region, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. The collector region for the other complementary transistor is formed within at least one other isolation region. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. To provide improved PNP transistor performance, the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer. FI 9-79-077

公开(公告)号：CA1142266A

公开(公告)日：1983-03-01

申请号：CA360337

申请日：1980-09-16

Applicant: IBM

Inventor： HORNG CHENG T ,  POPONIAK MICHAEL R ,  RUPPRECHT HANS S ,  SCHWENKER ROBERT O

IPC: H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/73 ,  H01L29/732 ,  H01L27/04

Abstract: A SELF-ALIGNED MICROMETER BIPOLAR TRANSISTOR DEVICE AND PROCESS A method for fabricating very high performance integrated circuit semiconductor devices. The method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. The fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultrahigh performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base. The P+ polysilicon layer which provides low base resistance is formed within the oxide isolation trenches, thus minimizing the parasitic capacitance. The transistor active base is formed in place by a low dosage boron implantation made with its concentration peak below the emitter. The device formed thus will have a controllable narrow base width and a FI9-79-021 low external base resistance. Both are essential to the high performance devices. The emitter of this invention structure is separated from the P+ polysilicon by a Si3N4/SiO2 composite dielectric layer. This dielectric separation ensures that electrons injected into the base do occur at the bottom of the emitter. The dielectric sleeve of the emitter also eliminates the sidewall hole current component normally existing in conventional transistors. Thus, the bipolar transistors formed by the disclosed process have a high emitter injection efficiency and also have high transistor current gains. Furthermore, the fabricated small geometry devices have planarized surface. The planarized device structure ensures the thin film covering which is critical to the integration of very small devices. FI 9-79-021

公开(公告)号：CA1043474A

公开(公告)日：1978-11-28

申请号：CA289545

申请日：1977-10-26

Applicant: IBM

Inventor： RUPPRECHT HANS S ,  SCHWENKER ROBERT O

IPC: H01L29/73 ,  G01Q70/00 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/331 ,  H01L21/78 ,  H01L21/461 ,  H01L21/425

Abstract: A METHOD OF HIGH CURRENT ION IMPLANTATION A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical insulation, thereby rendering the integrated circuit ineffective. The method involves forming in a layer of electrically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impurities, and in addition, forming openings through the insulative layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings. Then, a beam of ions having sufficient energy to implant ions in the exposed wafer in said chip area and kerf openings is directed at the wafer. The presence of the kerf openings avoids the problem of charge buildup. Then, the kerf area is removed by conventional dicing to separate the wafer into a plurality of chips.

公开(公告)号：FR2379163A1

公开(公告)日：1978-08-25

申请号：FR7739913

申请日：1977-12-23

Applicant: IBM

Inventor： RUPPRECHT HANS S ,  SCHWENKER ROBERT O

IPC: H01L29/73 ,  G01Q70/00 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/331 ,  H01L21/78

Abstract: A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical insulation, thereby rendering the integrated circuit ineffective. The method involves forming in a layer of electrically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impurities, and in addition, forming openings through the insulative layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings. Then, a beam of ions having sufficient energy to implant ions in the exposed wafer in said chip area and kerf openings is directed at the wafer. The presence of the kerf openings avoids the problem of charge buildup. Then, the kerf area is removed by conventional dicing to separate the wafer into a plurality of chips.