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    11.
    发明专利
    未知

    公开(公告)号：DE69031442D1

    公开(公告)日：1997-10-23

    申请号：DE69031442

    申请日：1990-06-21

    Applicant: IBM

    Inventor： JANCZYN JOYCE MARIE ,  MARKSTEIN PETER WILLY

    IPC: G06F9/45

    Abstract: The present invention relates to a method, in an optimising compiler using specified optimisation procedures for identifying ways of improving the quality of compiled code, for performing preliminary optimising procedures on a program to be compiled, prior to carrying out any specified optimisation procedure. According to the invention the preliminary optimising procedures comprise: (a) developing a control flowgraph representing all possible execution paths for the program; (b) identifying subgraphs in the program; (c) performing the steps of: (1) selecting a subgraph to be examined for the optimisation procedure, the first subgraph on a first iteration being the entire program; (2) by examining the code sequences in the subgraph, determining the number of entities in the subgraph which are relevant to each dimension of arrays used in the specified procedure to represent data flow equations; (3) determining the amount of memory required to contain the arrays; (4) if the amount of memory exceeds a predetermined memory usage limit for the compilation thereby denoting an unsuccessful attempt at the optimisation procedure, applying step (5) to the subgraph, otherwise applying the optimisation procedure to the subgraph, and (5) applying steps (2) to (4) for every subgraph contained in the subgraph for which insufficient memory was found in step (4). a

    14.
    发明专利
    未知

    公开(公告)号：DE3485929D1

    公开(公告)日：1992-10-29

    申请号：DE3485929

    申请日：1984-05-30

    Applicant: IBM

    Inventor： AUSLANDER MARC ALAN ,  COCKE JOHN ,  HAO HSIEH TUNG ,  MARKSTEIN PETER WILLY ,  RADIN GEORGE

    IPC: G06F9/30 ,  G06F7/493 ,  G06F7/50 ,  G06F9/302 ,  G06F9/305 ,  G06F9/32 ,  G06F9/46

    Abstract: @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.

    16.
    发明专利
    未知

    公开(公告)号：DE3685339D1

    公开(公告)日：1992-06-25

    申请号：DE3685339

    申请日：1986-01-24

    Applicant: IBM

    Inventor： CHAITIN GREGORY JOHN ,  HOPKINS MARTIN EDWARD ,  MARKSTEIN PETER WILLY ,  WARREN JR

    IPC: G06F9/45 ,  G06F9/44

    Abstract: A method for improving the quality of code generated by a compiler in terms of execution time, object code space, or both. The method is applicable to computers that have a redundancy of instructions, in that the same operation exists in forms that operate between registers, between main storage locations, and between registers and main storage. The method selects the best form of each such instruction to use, for the context in which the instruction lies.

    17.
    发明专利
    未知

    公开(公告)号：DE3582974D1

    公开(公告)日：1991-07-04

    申请号：DE3582974

    申请日：1985-07-08

    Applicant: IBM

    Inventor： AUSLANDER MARC ALAN ,  HOPKINS MARTIN EDWARD ,  MARKSTEIN PETER WILLY

    IPC: G06F9/44 ,  G06F9/45

    Abstract: A method operable within an optimizing compiler generating Basis items and Kill Sets for use during subsequent global common subexpressions elimination and code motion procedures. More particularly, the method comprises assigning a symbolic register to each non-basis element to be computed as follows: creating a tuple (v) for each computation which is to be converted to a machine instruction by the compiler creating a table (optimally, a hash table) having an entry for all the tuples in the program being compiled; for every Basis element in a tuple being entered in the table a symbolic register uniquely assigned to that tuple is added to the Kill Set for that Basis element. For every non-basis element "n" in the tuple being entered into the table, the uniquely assigned symbolic register for that tuple is added to the Kill Sets for all the Basis elements in whose Kill Sets that non-basis element "n" appears. The symbolic register assigned to the tuple in the table is chosen to total the result of the computation of the non-basis element; and finally, a second table is constructed so that given a symbolic register, the computation which it represents can be retrieved.

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